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IBM 4300 Manual page 250

Processors principles of operation for ecps: vse mode
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Interrupt Key
When the interrupt key is activated, an
external-interruption condition indicating the
interrupt key is generated. (See the section
"Interrupt Key" in Chapter 6, "Interruptions. ")
The interrupt key is effective when the CPU is
in the operating or stopped state.
It
depends on
the model whether the interrupt key is effective
when the CPU is in the load state.
Interval-Ti~er
l7ontrol
The interval-timer control disables or enables
operation of the interval timer. Disabling the
interval timer does not affect any other facility.
When the control is set to disable the interval
timer, updating of assigned storage locations 80-83
ceases. The contents of locations 80-83 remain at
the last value to which they were updated, unless
changed by a subsequent store operation. Any
already pending interval-timer-interruption
condition is kept pending without regard to the
state of the external mask, PSW bit 7, and the
interval-timer mask, bit 24 of control register O.
When the control is set to enable the interval
timer, updating of locations 80-83 is resumed using
the current contents.
If
an interval-timer-
interruption request existed and was kept pending
when the interval-timer control was last set to
disable, that condition remains pending until the
CPU is enabled for the interruption.
The setting to enable the interval timer is
considered the normal setting. The test indicator
mayor may not be turned on when the
interval-timer control is set to disable.
Programming Note
Disabling the interval timer allows execution of a
program which uses locations 80-83 as ordinary
storage. A program which does not use the interval
timer will function correctly with the interval timer
disabled, even when the interval timer fails.
Load Indicator
The load -indicator is on during initial program
loading, indicating that the CPU is in the load
state. The indicator goes on when the load-clear or
load-normal key is activated and the corresponding
operation is started.
It
goes off after the new PSW
is loaded successfully.
Load-l7lear Key
Activating the load-clear key causes a clear-reset
operation to be performed and initial program
loading to be started using the 110 device specified
by the load-unit-address controls. For details, see
the sections "Resets" and "Initial Program
Loading" in Chapter 4, "Control."
The load-clear key is effective when the CPU is
in the operating, stopped, load, or check-stop state.
Load-Nor~al
Key
Activating the load-normal key causes an initial-
program-reset operation to be performed and initial
program loading to be started using the 110 device
specified by the load-unit-address controls. For
details, see the sections "Resets" and "Initial
Program Loading" in Chapter 4, "Control."
The load-normal key is effective when the CPU
is in the operating, stopped, load, or check-stop
state.
Load-Unit-Address l7ontrols
The load-unit-address controls select three
hexadecimal digits, which provide the 12 rightmost
110
address bits used for initial program loading.
Machine-Save Key
Activating the machine-save key initiates a
machine-save operation. (See the section
"Machine Save" in Chapter 4, "Control. ") The
save indicator is turned on when the operation is
completed successfully.
The machine-save key is effective only when the
CPU is in the stopped state.
Operation Note
The machine-save operation may be used in
conjunction with a standalone dump program for
the analysis of major program malfunctions. For
such an operation, the following sequence would be
called for:
1.
Activation of the stop or system-reset-normal
key
2. Activation of the machine-save key
3. Activation of the load-normal key to enter a
standalone dump program
The system-reset-normal key must be activated
in step 1 when the stop key is not effective because
a continuous string of interruptions occurs or the
CPU is in the check-stop/state.
Manual Indicator
The manual indicator is on when the CPU is in the
stopped state. Some functions and several manual
controls are effective only when the CPU is in the
stopped state.
Chapter 13. Operator Facilities
13-3

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