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User's Manual
A2 Processor
A processor is assigned to one partition at any given time. A processor can be assigned to any given partition
without consideration of the physical configuration of the system (for example, shared registers, caches,
organization of the storage hierarchy), except that processors that share certain hypervisor resources might
need to be assigned to the same partition. Additionally, certain resources can be used by the guest at the
discretion of the hypervisor. Such usage might cause interference between partitions, and the hypervisor
should allocate those resources accordingly. The primary registers and facilities used to control logical parti-
tioning are described in the following subsections. Other facilities associated with logical partitioning are
described within the appropriate sections within this book.
Category Embedded.Hypervisor changes the operating system programming model to allow for easier virtu-
alization, while retaining a default backwards compatible mode where an operating system written for proces-
sors not containing this category will still operate as before without using the logical partitioning facilities.
2.2 Storage Addressing
As a 64-bit implementation of the Power ISA Architecture, the A2 core implements a uniform 64-bit effective
address (EA) space. Effective addresses are expanded into virtual addresses and then translated to 42-bit
(4 TB) real addresses by the memory management unit (see Memory Management on page 185 for more
information about the translation process). The organization of the real address space into a physical address
space is system-dependent, and is described in the user's manuals for chip-level products that incorporate an
A2 core.
The A2 core generates an effective address whenever it executes a storage access, branch, cache manage-
ment, or translation look aside buffer (TLB) management instruction, or when it fetches the next sequential
instruction.
2.2.1 Storage Operands
Bytes in storage are numbered consecutively starting with 0. Each number is the address of the corre-
sponding byte.
Data storage operands accessed by the integer load/store instructions can be bytes, halfwords, words,
doublewords or—for load/store multiple and string instructions—a sequence of words or bytes, respectively.
Data storage operands accessed by auxiliary execution unit (AXU) load/store instructions can be bytes, half-
words, words, doublewords, quadwords or double quadwords. The address of a storage operand is the
address of its first byte (that is, of its lowest-numbered byte). Byte ordering can be either big endian or little
endian, as controlled by the endian storage attribute (see Byte Ordering on page 66; also see Endian (E) on
page 197 for more information about the endian storage attribute).
Operand length is implicit for each scalar storage access instruction type (that is, each storage access
instruction type other than the load/store multiple and string instructions). The operand of such a scalar
storage access instruction has a "natural" alignment boundary equal to the operand length. In other words,
the natural address of an operand is an integral multiple of the operand length. A storage operand is said to
be aligned if it is aligned at its natural boundary; otherwise, it is said to be unaligned.
Data storage operands for storage access instructions have the characteristics shown in Table 2-1 on
page 63.
CPU Programming Model
Version 1.3
Page 62 of 864
October 23, 2012
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