Sony DNW-A100 Maintenance Manual page 160

4-1. DEC-65 Board (BKDW-505/506)
2. Pedestal Detect Timing Adjustment (For board suffix No.-11 only)
Perform this adjustment only when the board suffix No. of the DEC-65 board is -11.
(1) Connect as connection 2.
(2) Observe pin 7 of IC203 (G-6) with the oscilloscope.
. Oscilloscope setting
DC 200 mV/DIV, 1 us/DIV
CH-1:
Band-width limit: ON
(3) Adjust 1RV1 on the DUS-722 board that the pedestal detect timing satisfies the specifications.
For BKDW-505
7.40 to 7.50 us
Specification: Adjust the end of the burst signal to the
zero cross point within 7.40 to 7.50 us.
A B C
A B C
1
DECORDER
CLOCK GEN
2
3
EVR
4
5
6
7
4-6
Zero cross point
D E F G
D DEC-65E F G
1
2
3
4
DUS-722
ANALOG INPUT
RV1
5
6
IC203
7
For BKDW-506
7.45 to 7.55 us
Specification: Adjust the end of the burst signal within 7.45 to 7.55 us.
b
DNW-A100/A50/A45
DNW-A100P/A50P/A45P