Video Display Field 2 Vertical Blanking Start Register (Vdvblks2); Video Display Field 1 Vertical Blanking End Register (Vdvblke1) Field Descriptions; Video Display Field 2 Vertical Blanking Start Register (Vdvblks2) Field Descriptions - Texas Instruments TMS320DM648 User Manual

Video Display Registers
Table 4-11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions
(1)
Bit field symval
31-28 Reserved -
27-16 VBLNKYSTOP1 OF(value)
DEFAULT
15-12 Reserved -
11-0 VBLNKXSTOP1 OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_VDVBLKE1_field_symval

4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)

The video display field 2 vertical blanking start register (VDVBLKS2) controls the start of vertical blanking
in field 2.
In raw data mode, VBLNK is asserted whenever the frame line counter (FLCOUNT) is equal to
VBLNKYSTART2 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTART2 (this is shown in
Figure 4-6.
In BT.656 and Y/C mode, VBLNK is asserted whenever FLCOUNT = VBLNKYSTART2 and FPCOUNT =
VBLNKXSTART2. This VBLNK output control is completely independent of the timing control codes. The
V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.
The video display field 2 vertical blanking start register (VDVBLKS2) is shown in
described in Table
Figure 4-37. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
31 28
Reserved
R-0
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions
(1)
Bit field symval
31-28 Reserved -
27-16 VBLNKYSTART2 OF(value)
DEFAULT
15-12 Reserved -
(1)
For CSL implementation, use the notation VP_VDVBLKS2_field_symval
130 Video Display Port
(1)
Value BT.656 and Y/C Mode
0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh Specifies the line (in FLCOUNT) where Specifies the line (in FLCOUNT) where
VBLNK inactive edge occurs for field 1. vertical blanking ends (VBLNK inactive
Does not affect EAV/SAV V bit
operation.
0
0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh Specifies the pixel (in FPCOUNT)
where VBLNK inactive edge occurs for where vertical blanking ends (VBLNK
field 1.
0
4-12.
27
11
(1)
Value BT.656 and Y/C Mode
0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
0-FFFh Specifies the line (in FLCOUNT) where Specifies the line (in FLCOUNT) where
VBLNK active edge occurs for field 2.
Does not affect EAV/SAV V bit
operation.
0
0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
Description
Raw Data Mode
edge) for field 1.
Specifies the pixel (in FPCOUNT)
inactive edge) for field 1.
Figure 4-37
VBLNKYSTART2
R/W-0
VBLNKXSTART2
R/W-0
Description
Raw Data Mode
vertical blanking begins (VBLNK active
edge) for field 2.
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SPRUEM1 – May 2007