Clock Cycle Setting Of The F_Dp Communication; Response Times Of The F_Dp Communication - Siemens Sinumerik 840D sl Function Manual

Connecting Sensors/Actuators
7.4 Safety- -related CPU- -CPU communication (F_DP communication)
7.4.6

Clock cycle setting of the F_DP communication

MD $MN_SAFE_SRDP_IPO_TIME_RATIO can be used to set a reduction ratio to
the IPO clock cycle on the NCK side, this defines the time grid F_DP in which
communication takes place between the NCK and PLC (F_DP clock cycle). This
means that it is indirectly possible to optimize the utilization of the PLC using the
F_DP communication.
The following supplementary conditions apply:
S The maximum value of the F_DP clock cycle exceeded
The upper value of the F_DP clock cycle is actively limited. A parameterized
error (F_DP_clock cycle > 250 ms) results in Alarm 27300: "F_DP: Cycle time
%1 [ms] is too long".
S Response when OB40 clock cycle is > F_DP clock cycle
If the F_DP clock cycle is exceeded, then Alarm 27352 "F_DP: Communication
error %1, error %2" is not immediately output, but up to a maximum limit value
of 500 ms, an attempt is made to restart the OB40 coupling. In this case, the
IPO clock cycle is used as call cycle and no longer the F_DP clock cycle.
After the 500 ms limit has been exceeded, the alarm mentioned above is output
and the configured stop response (STOP D or E) is initiated. F_DP communica-
tion processing is stopped. The F_RECVDP drivers output fail--safe values (0)
as F net data.
S Displaying the maximum F_DP clock cycle
The maximum F_DP clock cycle that occurs is displayed in MD
$MN_INFO_SAFE_SRDP_CYCLE_TIME.
S Parameterizing error of the F_DP clock cycle
The lower value of the F_DP clock cycle is not actively limited. When setting
the F_DP clock cycle, the PLC--CPU performance should always be taken into
consideration.
When parameterizing an F_DP cycle that is too low, Alarm 27353: "F_DP:
Actual cycle time %1 [ms] > parameterized cycle time" is output specifying the
currently effective F_DP clock cycle.
The criterion for an F_DP clock cycle that is set too low is that the parame-
terized F_DP clock cycle was exceeded 100 times one after the other.
7.4.7

Response times of the F_DP communication

The response times listed here refer exclusively to the internal processing of the
signals by the F_DP communication layer. The following apply:
S T(FRDP - -> DB18) or T(FRDP - -> SPL- -INSE)
The transfer time from the input area of the F_RECVDP module to the input
interface of the PLC--SPL or NCK--SPL
S T(DB18 - -> FSDP) or T(SPL- -OUTSE - -> FSDP)
The transfer time from the output interface of the PLC--SPL or NCK--SPL to the
output area of the F_SENDDP.
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SINUMERIK 840D sl/SINAMICS S120 SINUMERIK Safety Integrated (FBSI sl) - - 10.2015 Edition
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