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U — Unstack 16-bit data. These cycles are extended to two bus cycles if the MCU is
V — Vector fetch. Vectors are always aligned 16-bit words. These cycles are extend-
t — 8-bit conditional read. These cycles are either data read cycles or free cycles,
T — 16-bit conditional read. These cycles are either data read cycles or free cycles,
x — 8-bit conditional write. These cycles are either data write cycles or free cycles,
PPP/P — Short branches require three cycles if taken, one cycle if not taken. Since the
OPPP/OPO — Long branches require four cycles if taken, three cycles if not taken. Optional cy-
CPU12
REFERENCE MANUAL
operating with an 8-bit external data bus and the SP is pointing to external mem-
ory. There can be additional stretching when the address space is assigned to
a chip-select circuit programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses to a memory that is not de-
signed for single-cycle misaligned access. The internal RAM is designed to al-
low single-cycle misaligned word access.
ed to two bus cycles if the MCU is operating with an 8-bit external data bus and
the program is stored in external memory. There can be additional stretching
when the address space is assigned to a chip-select circuit programmed for
slow memory.
depending upon the data and flow of the REVW instruction. These cycles are
only stretched when controlled by a chip-select circuit programmed for slow
memory.
depending upon the data and flow of the REV or REVW instruction. These cy-
cles are extended to two bus cycles if the MCU is operating with an 8-bit external
data bus and the corresponding data is stored in external memory. There can
be additional stretching when the address space is assigned to a chip-select cir-
cuit programmed for slow memory. These cycles are also stretched if they cor-
respond to misaligned accesses to a memory that is not designed for single-
cycle misaligned access.
depending upon the data and flow of the REV or REVW instruction. These cy-
cles are only stretched when controlled by a chip-select circuit programmed for
slow memory.
Special Notation for Branch Taken/Not Taken Cases
instruction consists of a single word containing both an opcode and an 8-bit off-
set, the not-taken case is simple — the queue advances, another program word
fetch is made, and execution continues with the next instruction. The taken case
requires that the queue be refilled so that execution can continue at a new ad-
dress. First, the effective address of the destination is determined, then the CPU
performs three program word fetches from that address.
cles are required because all long branches are page two opcodes, and thus
include the $18 prebyte. The CPU12 treats the prebyte as a special 1-byte in-
struction. If the prebyte is misaligned, the optional cycle is used to perform a pro-
gram word access; if the prebyte is aligned, the optional cycle is used to perform
a free cycle. As a result, both the taken and not-taken cases use one optional
cycle for the prebyte. In the not-taken case, the queue must advance so that ex-
ecution can continue with the next instruction, and another optional cycle is re-
quired to maintain the queue. The taken case requires that the queue be refilled
so that execution can continue at a new address. First, the effective address of
the destination is determined, then the CPU performs three program word fetch-
es from that address.
INSTRUCTION GLOSSARY
MOTOROLA
6-7
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