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There are four possible sources of reset. Power-on reset (POR) and external reset
share the same reset vector. The computer operating properly (COP) reset and the
clock monitor reset each have a vector.
7.3.1 Power-On Reset
The M68HC12 device integration module incorporates circuitry to detect a positive
transition in the V
asserting the reset signal internally. The signal is typically released after a delay that
allows the device clock generator to stabilize.
7.3.2 External Reset
The MCU distinguishes between internal and external resets by sensing how quickly
the signal on the RESET pin rises to logic level one after it has been asserted. When
the MCU senses any of the four reset conditions, internal circuitry drives the RESET
signal low for 16 clock cycles, then releases. Eight clock cycles later, the MCU sam-
ples the state of the signal applied to the RESET pin. If the signal is still low, an exter-
nal reset has occurred. If the signal is high, reset has been initiated internally by either
the COP system or the clock monitor.
7.3.3 COP Reset
The MCU includes a computer operating properly (COP) system to help protect
against software failures. When the COP is enabled, software must write a particular
code sequence to a specific address in order to keep a watchdog timer from timing out.
If software fails to execute the sequence properly, a reset occurs.
7.3.4 Clock Monitor Reset
The clock monitor circuit uses an internal RC circuit to determine whether clock fre-
quency is above a predetermined limit. If clock frequency falls below the limit when the
clock monitor is enabled, a reset occurs.
7.4 Interrupts
Each M68HC12 device can recognize a number of interrupt sources. Each source has
a vector in the vector table. The XIRQ signal, the unimplemented opcode trap, and the
SWI instruction are non-maskable, and have a fixed priority. The remaining interrupt
sources can be masked by the I bit. In most M68HC12 devices, the external interrupt
request pin is assigned the highest maskable interrupt priority, and the internal period-
ic real-time interrupt generator has the next highest priority. Other maskable interrupts
are associated with on-chip peripherals such as timers or serial ports. These maskable
sources have default priorities that follow the address order of the interrupt vectors.
The higher the vector address, the higher the priority of the interrupt. Typically, a de-
vice integration module incorporates logic that can give one maskable source priority
over other maskable sources.
CPU12
REFERENCE MANUAL
supply and initialize the device during cold starts, generally by
DD
EXCEPTION PROCESSING
MOTOROLA
7-3
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