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IDIVS
Operation:
(D)
Description:
Performs signed integer division of a signed 16-bit numerator in double
accumulator D by a signed 16-bit denominator in index register X, pro-
ducing a signed 16-bit quotient in X, and a signed 16-bit remainder in D.
If division by zero is attempted, the values in D and X are not changed,
but the values of the N, Z, and V status bits are undefined.
Other than division by zero, which is not legal and causes the C status
bit to be set, the only overflow case is:
But the highest positive value that can be represented in a 16-bit two's
complement number is 32,767 ($7FFFF).
Condition Codes and Boolean Formulas:
S
–
N:
Z:
V:
C:
Addressing Modes, Machine Code, and Execution Times:
Source Form
IDIVS
CPU12
REFERENCE MANUAL
Integer Divide (Signed)
÷
(X) ⇒ X; Remainder ⇒ D
$8000
–32,768
− − − − − − − − − − − − −
----------------- -
=
$FFFF
X
H
I
N
Z
∆
∆
–
–
–
Set if MSB of result is set; cleared otherwise. Undefined after over-
flow or division by zero.
Set if quotient is $0000; cleared otherwise. Undefined after overflow
or division by zero.
Set if the result was > $7FFF or < $8000; cleared otherwise. Unde-
fined after division by zero.
X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise.
Address Mode
INH
INSTRUCTION GLOSSARY
+32,768
=
–1
V
C
∆
∆
Object Code
18 15
IDIVS
Cycles
Access Detail
12
OffffffffffO
MOTOROLA
6-95
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