Table of Contents
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This is a complete revision and reprint. All known errors in the publication have been
corrected. The following summary lists significant changes.
Page
3-6
Additional information provided in Table 3-2.
3-9
Changed paragraph 3.8.6 to indicate accumulator offset is an unsigned value.
Changed paragraph 4.3.3.4 to show that both taken and not taken cases for loop primitives
4-5
use the same number of P cycles.
5-18
Table 5-22, operation sequence of RTI instruction modified to match sequence in Sec. 6.
6-3 and 6-4
Removed spurious letter "e" from "opr" source forms.
6-11 to 6-14
Added overbars to terms in Boolean formulae for ADCA, ADCB, ADDA, and ADDB.
6-27
Modified V bit description of condition code register.
6-70, 6-71, 6-92, 6-93,
Corrected access details for loop primitives to show that taken and not taken cases both
6-200 and 6-202
use three P cycles.
6-78, 6-79, 6-94
Correction in descriptions for EDIV, EDIVS, and IDIV: "dividend" is divided by "divisor."
6-78
Comment removed in EDIV description regarding C status bit.
6-81, 6-82, 6-83, 6-84,
In condition code C bit description of EMAXD, EMAXM, EMIND, EMINM, MAXA, MAXM,
6-139, 6-140, 6-142,
MINA, MINM, SUBA, SUBB and SUBD, two occurrences of the word "absolute" have been
6-143, 6-193, 6-194,
removed.
6-195
6-148
Overbar added to term in NEGA operation description.
6-167
Corrected access detail for REV instruction.
6-177
Corrected operation sequence for RTI instruction.
Corrected operation sequence for STOP instruction. Also, fourth paragraph of description
6-189
modified so as to not indicate that SP is changed.
6-196
Condition code register corrected; status bit I is set (1) following the SWI instruction.
6-213
Corrected operation sequence for WAI instruction.
6-214
Corrected access detail for WAV instruction.
Section 8.4.2, second paragraph, time-out of 256 E clock cycles is changed to 512 E clock
8-7
cycles. Fourth paragraph, "Nine target E-cycles later," is now "Ten target E-cycles later."
8-8
Figure 8-2, nine cycle reference is changed to ten cycles; art is modified accordingly.
Table 8-2, command order changed, footnote explanations added, ENTER_TAG_MODE
8-10
command deleted.
Section 8.4.4.1, reset conditions for STATUS register corrected. ITF bit name is changed
8-12
to ENTAG, Instruction Tagging Enable.
9-16 and 9-21
Corrected flow arrow and font substitution errors in Figures 9-9 and 9-10.
9-24
Changed paragraph 9.6.3. to reflect a three-cycle delay rather than a four-cycle delay.
9-25
Corrected flow arrow error and removed cycle 10.1 Figure 9-11.
9-28
Figure 9-12, Corrected inappropriate line break in code.
Table B-3, last row (EMACS) math operation corrected and two occurrences of
B-10
"per iteration" removed.
B-13
Section B.7.2, first sentence, "six transfer instructions" is now "eight transfer instructions."
Minor grammatical and typographic corrections to improve consistency and presentation.
General
New index markers.
CPU12
REFERENCE MANUAL
SUMMARY OF CHANGES
SUMMARY OF CHANGES
Change
MOTOROLA
S-1
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