Table of Contents
Advertisement
In the STAA 1,–SP example, the stack pointer is pre-decremented by one and then A
is stored to the address contained in the stack pointer. Similarly the LDX 2,SP+ first
loads X from the address in the stack pointer, then post-increments SP by two.
Example:
MOVW
This example demonstrates how to work with data structures larger than bytes and
words. With this instruction in a program loop, it is possible to move words of data from
a list having one word per entry into a second table that has four bytes per table ele-
ment. In this example the source pointer is updated after the data is read from memory
(post-increment) while the destination pointer is updated before it is used to access
memory (pre-increment).
3.8.6 Accumulator Offset Indexed Addressing
In this indexed addressing mode, the effective address is the sum of the values in the
base index register and an unsigned offset in one of the accumulators. The value in
the index register itself is not changed. The index register can be X, Y, SP, or PC and
the accumulator can be either of the 8-bit accumulators (A or B) or the 16-bit D accu-
mulator.
Example:
LDAA
This instruction internally adds B to X to form the address from which A will be loaded.
B and X are not changed by this instruction. This example is similar to the following
two-instruction combination in an M68HC11.
ABX
LDAA
However, this two-instruction sequence alters the index register. If this sequence was
part of a loop where B changed on each pass, the index register would have to be re-
loaded with the reference value on each loop pass. The use of LDAA B,X is more ef-
ficient in the CPU12.
3.8.7 Accumulator D Indirect Indexed Addressing
This indexed addressing mode adds the value in the D accumulator to the value in the
base index register to form the address of a memory location that contains a pointer
to the memory location affected by the instruction. The instruction operand does not
point to the address of the memory location to be acted upon, but rather to the location
of a pointer to the address to be acted upon. The square brackets distinguish this ad-
dressing mode from D accumulator offset indexing.
Example:
JMP
GO1
GO2
GO3
CPU12
REFERENCE MANUAL
2,X+,4,+Y
B,X
0,X
[D,PC]
DC.W
PLACE1
DC.W
PLACE2
DC.W
PLACE3
ADDRESSING MODES
MOTOROLA
3-9
Advertisement
Table of Contents
