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RTI
Operation:
(M
(SP)
(M
(SP)
(M
(SP)
(M
(SP)
(M
(SP)
Description:
Restores system context after interrupt service processing is completed.
The condition codes, accumulators B and A, index register X, the PC,
and index register Y are restored to a state pulled from the stack. The X
mask bit may be cleared as a result of an RTI instruction, but cannot be
set if it was cleared prior to execution of the RTI instruction.
If another interrupt is pending when RTI has finished restoring registers
from the stack, the SP is adjusted to preserve stack content, and the new
vector is fetched. This operation is functionally identical to the same op-
eration in the M68HC11, where registers actually are re-stacked, but is
faster.
Condition Codes and Boolean Formulas:
S
∆
Condition codes take on the value pulled from the stack, except that the X mask bit can-
not change from zero to one. Software can leave the X bit set, leave it cleared, or
change it from one to zero, but it can only be set by a reset or by recognition of an XIRQ
interrupt.
Addressing Modes, Machine Code, and Execution Times:
Source Form
RTI
(with interrupt pending)
CPU12
REFERENCE MANUAL
Return from Interrupt
) ⇒ CCR; (SP) + $0001 ⇒ SP
) ⇒ B : A; (SP) + $0002 ⇒ SP
: M
(SP + 1)
) ⇒ X
: M
(SP + 1)
H
) ⇒ PC
: M
(SP + 1)
H
) ⇒ Y
: M
(SP + 1)
H
X
H
I
N
Z
⇓
∆
∆
∆
∆
Address Mode
INH
0B
INSTRUCTION GLOSSARY
; (SP) + $0004 ⇒ SP
: X
L
; (SP) – $0002 ⇒ SP
: PC
L
; (SP) + $0004 ⇒ SP
: Y
L
V
C
∆
∆
Object Code
RTI
Cycles
Access Detail
8
uUUUUPPP
10
uUUUUVfPPP
MOTOROLA
6-177
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