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NEG instruction 6-147
NEGA instruction 6-148
Negate instructions 5-6, 6-147 to 6-149
Negated 1-3
Negative integers 2-5
NEGB instruction 6-149
Non-maskable interrupts 7-1 to 7-2, 7-4
NOP instruction 5-22, 6-150
Notation
Branch taken/not taken 6-7
Changes in CCR bits 6-2
Cycle-by-cycle operation 6-5
Memory and addressing 1-2
Object code 6-2
Operators 1-3
Source forms 6-3
System resources 1-2
Null operation instruction 5-22, 6-150
Numeric range of branch offsets 3-4
Object code notation 6-2
Odd bytes 2-5
Opcodes B-2, B-9
Map A-20
Operators 1-3
Optional cycles 4-4 to 4-5, 6-6
ORAA instruction 6-151
ORAB instruction 6-152
ORCC instruction 6-153
Orthogonality C-5
Pointer calculation instructions 5-20,
6-128 to 6-130
Pointers C-4
Postbyte 3-5, 6-90, 6-185, 6-203
Postbyte encoding
Exchange instructions A-24
Indexed addressing modes A-22
Loop primitive instruction A-25
Transfer instructions A-24
Post-decrement indexed addressing mode 3-8
Post-increment indexed addressing mode 3-8
Power conservation 5-21, 6-189, 6-213
Power-on reset 7-3
Pre-decrement indexed addressing mode 3-8
Pre-increment indexed addressing mode 3-8
Priority, exception 7-2
Program counter 2-1 to 2-2, 3-5, 6-31, 6-49, 6-52,
6-103, 6-128 to 6-130, 6-144 to 6-145, 6-150,
6-177 to 6-178, 6-196, 6-201, 6-205
Program word access cycle 6-6
Programming model 1-1, 2-1, B-3
MOTOROLA
I-6
O
P
Pseudo-non-maskable interrupt 7-2
PSHA instruction 6-154
PSHB instruction 6-155
PSHC instruction 6-156
PSHD instruction 6-157
PSHX instruction 6-158
PSHY instruction 6-159
PULA instruction 6-160
PULB instruction 6-161
PULC instruction 6-162
PULD instruction 6-163, C-2
Pull instructions C-5
PULX instruction 6-164
PULY instruction 6-165
Push instructions C-5
PUSHD instruction C-2
Range of mnemonics 1-3
Read indirect PPAGE cycle 6-5
Read PPAGE cycle 6-5
Read 8-bit data cycle 6-6
Read16-bit data cycle 6-6
Register designators 6-3
Relative addressing mode 3-4
Relative offset 3-4
Resets 7-1 to 7-2
Clock monitor 7-3
COP 7-3
External 7-3
Power-on 7-3
REV instruction 5-9, 6-166, 9-1, 9-5, 9-13 to 9-15,
9-17 to 9-20, 9-22, 9-29
REVW instruction 5-9, 6-168, 9-1, 9-5,
9-13 to 9-15, 9-17 to 9-20, 9-22, 9-29
ROL instruction 6-170
ROLA instruction 6-171
ROLB instruction 6-172
ROM, BDM 8-6
ROR instruction 6-173
RORA instruction 6-174
RORB instruction 6-175
Rotate instructions 5-8, 6-170 to 6-175
RTC instruction 3-12, 4-3, 5-17, 6-176,
10-2 to 10-3, B-16, C-4 to C-5
RTI instruction 2-4, 5-18, 6-177, 7-5
RTS instruction 4-3, 6-178
S control bit 2-3, 6-189
SBA instruction 6-179
SBCA instruction 6-180
SBCB instruction 6-181
SEC instruction 6-182
R
S
CPU12
REFERENCE MANUAL
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