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Instructions 5-9, 6-141, 6-166, 6-168, 6-214, 9-1,
9-9, 9-13 to 9-14, 9-17 to 9-19, 9-22, B-14
Interrupts 9-20, 9-23 to 9-24, 9-26
Knowledge base 9-2, 9-5
Membership functions 5-9, 6-141, 9-1 to 9-3,
9-9 to 9-13, 9-26 to 9-27
Outputs 5-9, 9-30
Rule evaluation 5-9, 6-166, 6-168, 9-1, 9-5,
9-13 to 9-15, 9-17 to 9-20, 9-22, 9-29
Rules 9-2, 9-5
Sets 9-2
Tabular membership functions 5-12, 9-26
Weighted average 5-9, 6-214, 9-1, 9-6,
9-22 to 9-24, 9-26
General purpose accumulators 2-1
H status bit 2-4, 6-8, 6-11 to 6-14, 6-69
High-level language C-1, C-3
Addressing modes C-1, C-3 to C-4
Condition codes register C-4
Expanded memory C-4 to C-5
Instructions C-1
Loop primitives C-3
Stack C-1 to C-2
I mask bit 2-4, 6-18, 6-55, 6-183, 6-196, 6-205,
6-213, 7-2
IBEQ instruction 6-92, A-25
IBNE A-25
IBNE instruction 6-93
IDIV instruction 6-94
IDIVS instruction 6-95, C-3
Immediate addressing mode 3-2
INC instruction 6-96
INCA instruction 6-97
INCB instruction 6-98
Increment instructions 5-4, 6-96 to 6-101
Index calculation instructions 5-20, 6-9 to 6-10,
6-76 to 6-77, 6-100 to 6-101, 6-129 to 6-130,
B-11
Index manipulation instructions 5-19, 6-67 to 6-68,
6-90, 6-126 to 6-127, 6-158 to 6-159,
6-164 to 6-165, 6-191 to 6-192, 6-203,
6-209 to 6-212, 6-215 to 6-216
Index registers 2-1 to 2-2, 5-19, C-2
X 3-5, 6-9, 6-67, 6-70 to 6-71, 6-76, 6-90 to 6-95,
6-100, 6-126, 6-128 to 6-130, 6-158, 6-164,
6-166, 6-168, 6-177, 6-185, 6-191, 6-196,
6-200 to 6-203, 6-209, 6-211, 6-215
Y 3-5, 6-10, 6-68, 6-70 to 6-71, 6-77 to 6-80,
MOTOROLA
I-4
G
H
I
6-85 to 6-86, 6-90, 6-92 to 6-93, 6-101,
6-127 to 6-130, 6-159, 6-165 to 6-166,
6-168, 6-177, 6-185, 6-192, 6-196,
6-200 to 6-203, 6-210, 6-212, 6-216
Indexed addressing modes 2-2, 3-5, A-22,
B-6 to B-9
Accumulator direct 3-9
Accumulator offset 3-9
Automatic indexing 3-8
Base index register 3-6, 3-10
Extension byte 3-5
Postbyte 3-5
Postbyte encoding 3-5, A-22
16-bit constant indirect 3-7
16-bit constant offset 3-7
5-bit constant offset 3-6
9-bit constant offset 3-7
Inference kernel, fuzzy logic 9-7
Inherent addressing mode 3-2
INS instruction 6-99
Instruction queue 1-1, 2-5, 4-1, 8-1, B-4
Alignment 4-1
Buffer 4-1
Debugging 8-1
Movement cycles 4-2
Reconstruction 8-1, 8-3, 8-5
Stages 4-1, 8-1
Status registers 8-4 to 8-5
Status signals 4-1, 8-1 to 8-3, 8-5 to 8-6
Instruction set A-2
Integer division 5-7
Interrupt instructions 5-18
Interrupts 7-3
Enabling and disabling 2-3 to 2-4, 6-55, 6-183,
7-2
External 7-5
I mask bit 2-4, 6-55, 6-183, 6-196, 6-213, 7-4
Instructions 5-18, 6-55, 6-177, 6-183, 6-196,
6-205
Low-power stop 5-21, 6-189
Maskable 2-4, 7-4
Non-maskable 2-3, 7-2, 7-4
Recognition 7-4
Return 2-4, 5-18, 6-177, 7-5
Service routines 7-4
Software 5-18, 6-196, 7-1, 7-6
Stacking 7-4
Vectors 7-3
Wait instruction 5-21, 6-213
X mask bit 2-3, 6-189, 6-213, 7-4
INX instruction 6-100
INY instruction 6-101
CPU12
REFERENCE MANUAL
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