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Command
GO
TRACE1
TAGGO
WRITE_NEXT
WRITE_PC
WRITE_D
WRITE_X
WRITE_Y
WRITE_SP
READ_NEXT
READ_PC
READ_D
READ_X
READ_Y
READ_SP
8.4.4 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address space when
BDM is active. Mapping is shown in
Address
$FF00
$FF01
$FF02–$FF03
$FF04–$FF05
$FF06
The content of the instruction register is determined by the type of background instruc-
tion being executed. The status register indicates BDM operating conditions. The shift
register contains data being received or transmitted via the serial interface. The ad-
dress register is temporary storage for BDM commands. The CCR register preserves
the content of the CPU12 CCR while BDM is active.
The only register of interest to users is the status register. The other BDM registers are
used only by the BDM firmware to execute commands. The registers can be accessed
by means of the hardware READ_BD and WRITE_BD commands, but must not be
written during BDM operation.
CPU12
REFERENCE MANUAL
Table 8-3 BDM Firmware Commands
Opcode (Hex)
Data
08
none
10
none
18
none
42
16-bit data in
43
16-bit data in
44
16-bit data in
45
16-bit data in
46
16-bit data in
47
16-bit data in
62
16-bit data out
63
16-bit data out
64
16-bit data out
65
16-bit data out
66
16-bit data out
67
16-bit data out
Table
Table 8-4 BDM Register Mapping
DEVELOPMENT AND DEBUG SUPPORT
Description
Resume normal processing
Execute one user instruction then return to BDM
Enable tagging then resume normal processing
X = X + 2; Write next word @ 0,X
Write program counter
Write D accumulator
Write X index register
Write Y index register
Write stack pointer
X = X + 2; Read next word @ 0,X
Read program counter
Read D accumulator
Read X index register
Read Y index register
Read stack pointer
8-4.
Register
BDM instruction register
BDM status register
BDM shift register
BDM address register
BDM CCR register
MOTOROLA
8-11
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