Page 1 MVME3600/4600 Series VME Processor Modules Programmer’s Reference Guide V36V46A/PG3 August 2001 Edition...
Page 2 ™ PowerPC is a registered trademark and PowerPC 604 is a trademark of International Business Machines Corporation and are used by Motorola, Inc. under license from International Business Machines Corporation. ® is a registered trademark of International Business Machines Corporation.
Page 3 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Page 4 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Page 6 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
Page 7: Table Of Contents
Contents About This Manual Summary of Changes ....................xx Overview of Contents ....................xx Comments and Suggestions ..................xxi Conventions Used in This Manual................xxi CHAPTER 1 Board Description and Memory Maps Introduction........................1-1 Overview......................1-1 Summary of Features ..................1-2 Block Diagrams ....................1-3 Functional Description....................1-7 Overview......................1-7 Programming Model ....................1-8 Memory Maps.....................1-8...
Page 8 Location Monitor Upper Base Address Register ........1-40 Location Monitor Lower Base Address Register........1-40 Semaphore Register 1 ................1-41 Semaphore Register 2 ................1-41 VME Geographical Address Register (VGAR) ........1-42 Z85230 ESCC and Z8536 CIO Registers and Port Pins ........1-43 Z8536/Z85230 Registers ................
Page 9 Prescaler Adjust Register................2-36 MPC Error Enable Register ...............2-36 MPC Error Status Register ................2-39 MPC Error Address Register ..............2-41 MPC Error Attribute Register - MERAT ..........2-41 PCI Interrupt Acknowledge Register ............2-43 MPC Slave Address (0,1 and 2) Registers ..........2-43 MPC Slave Address (3) Register...............2-44 MPC Slave Offset/Attribute (0,1 and 2) Registers ........2-45 MPC Slave Offset/Attribute (3) Registers..........2-46 General Purpose Registers.................2-47...
Page 10 MPIC Registers ....................2-68 RavenMPIC Registers ................2-68 Feature Reporting Register ............... 2-72 Global Configuration Register ..............2-73 Vendor Identification Register ..............2-74 Processor Init Register ................2-74 IPI Vector/Priority Registers..............2-75 Spurious Vector Register ................2-76 Timer Frequency Register................. 2-76 Timer Current Count Registers ..............
Page 11 DRAM Speeds .....................3-7 ROM/Flash Speeds ..................3-11 PowerPC 60x Bus Interface................3-12 Responding to Address Transfers..............3-12 Completing Data Transfers................3-12 Cache Coherency ..................3-12 Cache Coherency Restrictions..............3-13 L2 Cache Support ..................3-13 ECC........................3-13 Cycle Types ....................3-13 Error Reporting..................3-13 Error Logging ....................3-15 DRAM Tester....................3-15 ROM/Flash Interface ..................3-15 Refresh/Scrub....................3-19 Blocks A and/or B Present, Blocks C and D Not Present ......3-19 Blocks A and/or B Present, Blocks C and/or D Present......3-20...
Page 12 Universe Chip Problems after a PCI Reset.............. 4-13 Problem Description..................4-13 Examples ......................4-15 Example 1: MVME2600 Series Board Exhibits Problem......4-15 Example 2: MVME3600 Series Board Acts Differently ......4-17 Example 3: Universe Chip is Checked at Tundra ........4-19 CHAPTER 5 Programming Details Introduction .......................
Page 13 Endian Issues ......................5-11 Processor/Memory Domain ................5-14 Raven’s Involvement ..................5-14 PCI Domain ......................5-14 PCI-SCSI ....................5-14 PCI-Ethernet ....................5-15 PCI-Graphics .....................5-15 Universe’s Involvement ..................5-15 VMEbus Domain ....................5-15 ROM/Flash Initialization ..................5-16 APPENDIX A Related Documentation Motorola Computer Group Documents ..............A-1 Manufacturers’ Documents..................A-2 Related Specifications....................A-4 xiii...
Page 15 List of Figures Figure 1-1. MVME3600 Series System Block Diagram ...........1-5 Figure 1-2. MVME4600 Series System Block Diagram ...........1-6 Figure 1-3. VMEbus Master Mapping..............1-21 Figure 1-4. VMEbus Slave Mapping ...............1-23 Figure 2-1. Raven Block Diagram ................2-3 Figure 2-2. MPC to PCI Address Decoding ..............2-5 Figure 2-3.
Page 17 List of Tables Table 1-1. MVME3600/4600 Series Features Summary ...........1-2 Table 1-2. Default Processor Memory Map...............1-9 Table 1-3. CHRP Memory Map Example..............1-10 Table 1-4. Raven MPC Register Values for CHRP Memory Map......1-11 Table 1-5. PREP Memory Map Example..............1-12 Table 1-6. Raven MPC Register Values for PREP Memory Map ......1-13 Table 1-7.
Page 18 Table 5-4. Reset Sources and Devices Affected ............5-8 Table 5-5. Error Notification and Handling............. 5-10 Table 5-6. ROM/Flash Bank Default..............5-16 Table A-1. Motorola Computer Group Documents ..........A-1 Table A-2. Manufacturers’ Documents ..............A-2 Table A-3. Related Specifications ................A-4...
Page 19 About This Manual This manual provides programming information for the MVME3604 and MVME4604 VME Processor Modules (VMEmodules), that are based on the MVME3604-xxxx base board, the PM604-xxxx mezzanine modules, and the RAM201-xxx mezzanine modules. Extensive programming information is provided for several Application-Specific Integrated Circuit (ASIC) devices used on the boards.
Page 20: Summary Of Changes
Summary of Changes This is the third edition of the Programmer’s Reference Guide. It supersedes the January 2001 edition and incorporates the following updates. Date Description of Change August 2001 All data referring to the VME CSR Bit Set Register (VCSR_SET) and VME CSR Bit Clear Register (VCSR_CLR) has been deleted.
Page 21: Comments And Suggestions
Documentation, lists all documentation related to the MVME3600/4600 series. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:...
Page 22 bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
Page 23 The terms control bit, status bit, true, and false are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls.
Page 25: Introduction
This chapter briefly describes the board level hardware features of the MVME3600 series and MVME4600 series VME Processor Modules. The chapter begins with a board level overview and features list. Memory maps are next, and are the major feature of this chapter.
Page 26: Summary Of Features
Board Description and Memory Maps Mixing of MVME3600/4600 base and processor/memory modules with MVME160x processor/memory and base modules is NOT supported. Motorola cannot predict or guarantee the performance of any such mixture of Caution modules. Summary of Features There are many models based on the MVME3600/4600 series architecture.
Page 27: Block Diagrams
DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the MPIC interrupt controller. PCI devices include: SCSI, VME, graphics, Ethernet, and one PMC slot. Standard I/O functions are provided by the Super I/O device which resides on the ISA bus. The NVRAM/RTC and the http://www.motorola.com/computer/literature...
Page 28 Board Description and Memory Maps optional synchronous serial ports also reside on the ISA bus. The general system block diagrams for the MVME3600 series and the MVME4600 series are shown below: Computer Group Literature Center Web Site...
Page 29: Figure 1-1. Mvme3600 Series System Block Diagram
DRAM GRAPHICS ETHERNET SCSI VME BRIDGE CL-GD54XX W83C553 DEC21140 53C825A UNIVERSE REGISTERS AUI/10BT/100BTX BUFFERS RTC/NVRAM/WD MK48T559 SUPER I/O ESCC PC87308 85230 Z8536 712/761 P2 I/O OPTIONS VME P2 VME P1 BASE BOARD Figure 1-1. MVME3600 Series System Block Diagram http://www.motorola.com/computer/literature...
Page 30: Figure 1-2. Mvme4600 Series System Block Diagram
Board Description and Memory Maps PROCESSOR/MEMORY MEZZANINE MEMORY EXPANSION CONNECTORS CLOCK DEBUG CONNECTOR (64MB-1GB DRAM ON MEZZANINE) GENERATOR Flash L2 CACHE 256K Flash 4MB or 8MB PROCESSOR 0 MPC604 DRAM SYSTEM 64MB REGISTERS PROCESSOR 1 SECONDARY MPC604 ETHERNET AND SCSI MEMORY CONTROLLER PHB &...
Page 31: Functional Description
LEDs. All signals for the serial ports, the P1284/printer port, the SCSI interface, and the Ethernet interface are routed to P2. There are two P2 I/O options supported by the MVME3600 series and the MVME4600 series: MVME712M mode and MVME761 mode. The MVME761 mode provides an enhanced P1284 parallel port interface and full synchronous support for Serial Ports 3 and 4.
Page 32: Programming Model
Board Description and Memory Maps computers (SBCs). In either mode, 16-bit SCSI capability can only be used by systems with 5-row DIN support because the additional 8 bits of SCSI data lines reside on row Z of P2. The MVME3600/4600 series contains one IEEE1386.1 PCI Mezzanine Card (PMC) slot.
Page 33: Table 1-2. Default Processor Memory Map
2. The first 1MB of ROM/Flash Bank A appears at this range after a reset if the rom_b_rv control bit in the Falcon chip is cleared and the rom_a_rv control bit is set. If the rom_b_rv control bit is set then this address range maps to ROM/Flash Bank B. http://www.motorola.com/computer/literature...
Page 34: Table 1-3. Chrp Memory Map Example
Board Description and Memory Maps Processor CHRP Memory Map The following table shows a recommended CHRP memory map from the point of view of the processor. Table 1-3. CHRP Memory Map Example Processor Address Size Definition Start System Memory (onboard DRAM) 0000 0000 top_dram dram_size...
Page 35: Table 1-4. Raven Mpc Register Values For Chrp Memory Map
Table 1-4. Raven MPC Register Values for CHRP Memory Map Address Register Name Register Value FEFF 0040 MSADD0 4000 FCFF FEFF 0044 MSOFF0 & MSATT0 0000 00C2 FEFF 0048 MSADD1 FD00 FDFF FEFF 004C MSOFF1 & MSATT1 0300 00C2 FEFF 0050 MSADD2 0000 0000 http://www.motorola.com/computer/literature 1-11...
Page 36: Table 1-5. Prep Memory Map Example
Board Description and Memory Maps Table 1-4. Raven MPC Register Values for CHRP Memory Map (Continued) Address Register Name Register Value FEFF 0054 MSOFF2 & MSATT2 0000 0002 FEFF 0058 MSADD3 FE00 FE7F FEFF 005C MSOFF3 & MSATT3 0200 00C0 Processor PREP Memory Map The Raven/Falcon chipset can be programmed for a PREP-compatible memory map.
Page 37: Table 1-6. Raven Mpc Register Values For Prep Memory Map
4000 00C2 MSADD1 FEFF 0048 0000 0000 MSOFF1 & MSATT1 FEFF 004C 0000 0002 MSADD2 FEFF 0050 0000 0000 MSOFF2 & MSATT2 FEFF 0054 0000 0002 MSADD3 FEFF 0058 8000 BFFF MSOFF3 & MSATT3 FEFF 005C 8000 00C0 http://www.motorola.com/computer/literature 1-13...
Page 38: Pci Memory Maps
Board Description and Memory Maps PCI Configuration Access PCI Configuration accesses are accomplished via the CONFIG_ADD and CONFIG_DAT registers. These two registers are implemented by the Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC, respectively.
Page 39 3. Programmable mapping via the four PCI Slave Images in the Universe ASIC. 4. Programmable mapping via the Special Slave Image (SLSI) in the Universe ASIC. The following table shows the programmed values for the associated Raven PCI registers for the PCI CHRP memory map. http://www.motorola.com/computer/literature 1-15...
Page 40: Table 1-8. Raven Pci Register Values For Chrp Memory Map
Board Description and Memory Maps Table 1-8. Raven PCI Register Values for CHRP Memory Map Configuration Configuration Register Value Register Value Address Offset Register Name (Aliasing OFF) (Aliasing ON) RavenMPIC MBASE FC00 0000 FC00 0000 PSADD0 0000 3FFF 0100 3FFF PSOFF0 &...
Page 41: Table 1-10. Pci Prep Memory Map
128M VMEbus A32/D16 (Super/Program) 3800 0000 38FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 38FF 0000 38FF FFFF VMEbus A16/D16 (Super/Program) 3900 0000 39FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 39FF 0000 39FF FFFF VMEbus A16/D32 (Super/Data) http://www.motorola.com/computer/literature 1-17...
Page 42 Board Description and Memory Maps Table 1-10. PCI PREP Memory Map (Continued) PCI Address Size Definition Notes Start 3A00 0000 3AFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 3AFF 0000 3AFF FFFF VMEbus A16/D16 (User/Program) 3B00 0000 3BFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 3BFF 0000 3BFF FFFF...
Page 43: Table 1-11. Raven Pci Register Values For Prep Memory Map
Register Value Address Offset Register Name $100 LSI0_CTL C082 5100 $104 LSI0_BS 0100 0000 $108 LSI0_BD 3000 0000 $10C LSI0_TO XXXX 0000 $114 LSI1_CTL C042 5100 $118 LSI1_BS 3000 0000 $11C LSI1_BD 3800 0000 $120 LSI1_TO XXXX 0000 http://www.motorola.com/computer/literature 1-19...
Page 44: Vmebus Mapping
Board Description and Memory Maps Table 1-12. Universe PCI Register Values for PREP Memory Map Configuration Configuration Register Value Address Offset Register Name $128 LSI2_CTL 0000 0000 $12C LSI2_BS XXXX XXXX $130 LSI2_BD XXXX XXXX $134 LSI2_TO XXXX XXXX $13C LSI3_CTL 0000 0000 $140...
Page 45: Figure 1-3. Vmebus Master Mapping
NOTE 1 PCI MEMORY SPACE VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 VME A24 I/O SPACE VME A16 RESOURCES 11553.00 9609 Figure 1-3. VMEbus Master Mapping http://www.motorola.com/computer/literature 1-21...
Page 46 Board Description and Memory Maps Notes 1. Programmable mapping done by the Raven ASIC. 2. Programmable mapping via the four PCI Slave Images in the Universe ASIC. 3. Programmable mapping via the Special Slave Image (SLSI) in the Universe ASIC. VMEbus Slave Map The four programmable VME Slave Images in the Universe ASIC allow other VMEbus masters to get to any devices on the MVME3600/4600...
Page 47: Figure 1-4. Vmebus Slave Mapping
1896 9609 Figure 1-4. VMEbus Slave Mapping Notes 1. Programmable mapping via the four VME Slave Images in the Universe ASIC. 2. Programmable mapping via PCI Slave Images in the Raven ASIC. 3. Fixed mapping via the PIB device. http://www.motorola.com/computer/literature 1-23...
Page 48: Table 1-13. Universe Pci Register Values For Vmebus Slave Map Example
Board Description and Memory Maps The following table shows the programmed values for the associated Universe registers for the VMEbus slave function. Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example Configuration Configuration Register Value Register Value Address Offset Register Name (CHRP) (PREP)
Page 49: Falcon-Controlled System Registers
Table 1-15. System Register Summary BIT # ----> System Configuration Register (Upper Falcon’s PR_STAT1) FEF80400 Memory Configuration Register (Lower Falcon’s PR_STAT1) FEF80404 System External Cache FEF88000 Control Register CPU Control Register FEF88300 The following subsections describe these system registers in detail. http://www.motorola.com/computer/literature 1-25...
Page 50: System Configuration Register (Syscr)
System Identification. This field specifies the type of the overall system configuration so that the software may appropriately handle any software visible differences. For the MVME3600 series and the MVME4600 series, this field returns a value of $FE. SYSCLK System Clock Speed. This field relays the system clock...
Page 51: Memory Configuration Register (Memcr)
Falcon chip at a rising edge of the power- up reset and stored in this Memory Configuration Register to provide some information about the system memory. Configuration is accomplished with external pull-down resistors. This 32-bit read-only register is defined as follows: http://www.motorola.com/computer/literature 1-27...
Page 52 Board Description and Memory Maps Memory Configuration Register - $FEF80404 FIELD OPER RESET M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it indicates that a DRAM block requires faster refresh rate. If any of the four blocks requires faster refresh rate then the ram ref control bit should be set.
Page 53: System External Cache Control Register (Sxccr)
System External Cache Enable. When this bit is cleared, it disables this cache from responding to any bus cycles. SXC_FLSH_ System External Cache Flush. When this bit is pulsed true for at least 8 clock periods, it causes the system external http://www.motorola.com/computer/literature 1-29...
Page 54 Board Description and Memory Maps cache to write back dirty cache lines out to system memory and clears all the tag valid bits. This operation causes the Glance pair to request and hold the MPC bus until it has completed the flush operation (approximately 4100 clock cycles).
Page 55: Cpu Control Register
TBEN pin of Processor 0/1 will be driven low. ISA Local Resource Bus W83C553 PIB Registers The PIB contains ISA Bridge I/O registers for various functions. These registers are actually accessible from the PCI bus. Refer to the W83C553 Data Book for details. http://www.motorola.com/computer/literature 1-31...
Page 56: Pc87308Vul Super I/O (Isasio) Strapping
Board Description and Memory Maps PC87308VUL Super I/O (ISASIO) Strapping The PC87308VUL Super I/O (ISASIO) provides the following functions to the MVME3600/4600 series: a keyboard interface, a PS/2 mouse interface, a PS/2 floppy port, two async serial ports and a parallel port. Refer to the PC87308VUL Data Sheet for additional details and programming information.
Page 57: Module Configuration And Status Registers
These registers are listed in the following table: Table 1-18. Module Configuration and Status Registers PCI I/O Address Function 0000 0800 CPU Configuration Register 0000 0802 Base Module Feature Register 0000 0803 Base Module Status Register 0000 08C0 - 0000 08C1 Seven-Segment Display Register http://www.motorola.com/computer/literature 1-33...
Page 58: Cpu Configuration Register
Board Description and Memory Maps The following subsections describe these registers in detail. CPU Configuration Register The CPU Configuration Register is an 8-bit register located at ISA I/O address x0800. This register is defined for the MVME3600/4600 series to provide some backward compatibility with older MVME1600 products. The Base Module Status Register should be used to identify the base module type and the System Configuration Register should be used to obtain information about the overall system.
Page 59: Base Module Status Register (Bmsr)
SCSI Present. If set, there is no on-board SCSI interface. If cleared, on-board SCSI is supported. Base Module Status Register (BMSR) The Base Module Status Register is an 8-bit read-only register located at ISA I/O address x0803. Base Module Status Register - Offset $0803 FIELD BASE_TYPE OPER http://www.motorola.com/computer/literature 1-35...
Page 60: Seven-Segment Display Register
Board Description and Memory Maps Base Module Status Register - Offset $0803 RESET BASE_TYPE Base Module Type. This eight bit field is used to provide the category of the base module and is defined as follows: BASE_TYPE Value Base Module Type Reserved $0 to $F9 Reserved -- Special...
Page 61: Vme Registers
VMEbus Location Monitor Upper Base Address 0000 1003 VMEbus Location Monitor Lower Base Address 0000 1004 VMEbus Semaphore Register 1 0000 1005 VMEbus Semaphore Register 2 0000 1006 VMEbus Geographical Address Status These registers are described in the following subsections. http://www.motorola.com/computer/literature 1-37...
Page 62 Board Description and Memory Maps LM/SIG Control Register The LM/SIG Control Register is an 8-bit register located at ISA I/O address x1000. This register provides a method to generate software interrupts. The Universe ASIC is programmed so that this register can be accessed from the VMEbus to generate software interrupts to the processor(s).
Page 63 1 to the CLR_LM1 control bit. SIG0 SIG0 status bit. This bit can only be set by the SET_LM0 control bit. It can only be cleared by a reset or by writing a 1 to the CLR_LM0 control bit. http://www.motorola.com/computer/literature 1-39...
Page 64: Location Monitor Upper Base Address Register
Board Description and Memory Maps LM1 status bit. This bit can be set by either the location monitor function or the SET_LM1 control bit. LM1 correspond to offset 3 from the location monitor base address. This bit can only be cleared by a reset or by writing a 1 to the CLR_LM1 control bit.
Page 65: Semaphore Register 1
The Semaphore Register 2 is an 8-bit register located at ISA I/O address x1005. The Universe ASIC is programmed so that this register can be accessible from the VMEbus. This register can only be updated if bit 7 is http://www.motorola.com/computer/literature 1-41...
Page 66: Vme Geographical Address Register (Vgar)
Board Description and Memory Maps low or if the new value has the most significant bit cleared. When bit 7 is high, this register will not latch in the new value if the new value has the most significant bit set. Semaphore Register 2 - Offset $1005 FIELD SEM2...
Page 67: Z85230 Escc And Z8536 Cio Registers And Port Pins
Z85230: Port A (Serial Port 3) Data 0000 0844 Z8536 CIO: Port C’s Data Register 0000 0845 Z8536 CIO: Port B’s Data Register 0000 0846 Z8536 CIO: Port A’s Data Register 0000 0847 Z8536 CIO: Control Register 0000 084F Z85230/Z8536 Pseudo IACK http://www.motorola.com/computer/literature 1-43...
Page 68: Z8536 Cio Port Pins
Board Description and Memory Maps Z8536 CIO Port Pins The assignment for the Port pins of the Z8536 CIO is as follows: Table 1-21. Z8536 CIO Port Pins Assignment Port Signal Direction Descriptions Name TM3_ Port 3 Test Mode when IDREQ_ = 1; Input MID0 Module ID Bit 0 when IDREQ_ = 0.
Page 69: Table 1-22. Interpretation Of Mid3-Mid0
Module 3: EIA232 DCE 01-W3876B01 Module 3: EIA232 DTE 01-W3877B01 Module 3: EIA530 DCE 01-W3878B01 Module 3: EIA530 DTE 01-W3879B01 Module 3 Not Installed Module 4: EIA232 DCE 01-W3876B01 Module 4: EIA232 DTE 01-W3877B01 Module 4: EIA530 DCE 01-W3878B01 http://www.motorola.com/computer/literature 1-45...
Page 70: Isa Dma Channels
Board Description and Memory Maps Table 1-22. Interpretation of MID3-MID0 (Continued) Module LLB3_ IDREQ_ Serial Module Type Assembly MODSEL Number Module 4: EIA530 DTE 01-W3879B01 Module 4 Not Installed Note Because IDREQ_ and MID3-MID0 signals go through the P2MX (P2 multiplexing) function used on MVME3600/4600 series modules configured for the MVME761-type transition module, software must wait for the MID3-MID0 to become valid after asserting IDREQ_.
Page 71: Table 1-23. Pib Dma Channel Assignments
Serial Port 4 Transmitter (Z85230 Port B Tx) Channel 7 Not Used Lowest Note Because the Z85230 is an 8-bit device and Channels 5 and 6 are 16-bit DMA Channels, only every other byte (the even bytes) from memory is valid. http://www.motorola.com/computer/literature 1-47...
Page 73: Chapter 2 Raven Pci Host Bridge & Multi-Processor
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Introduction This chapter describes the architecture and usage of the Raven, a PowerPC to PCI Local Bus Bridge ASIC. The Raven is intended to provide PowerPC 60x (MPC60x) compliant devices access to devices residing on the PCI Local Bus.
Page 74: Block Diagram
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Function Features Interrupt Controller MPIC compliant Support for 16 external interrupt sources and two processors Multiprocessor interrupt control allowing any interrupt source to be directed to either processor Multilevel cross processor interrupt control for multiprocessor synchronization Four 31-bit tick timers Two 64-bit general purpose registers for cross-processor...
Page 75 PCI Bus Raven MPIC PCI Slave PCI Master PCI Dec PCI Regs PCIADIN Data Path ‘A’ Mux PCI FIFO Endian MPCADIN Data Path ‘B’ Mux MPC FIFO Endian MPC Slave MPC Dec MPC Regs MPC Master MPC Bus...
Page 76: Functional Description
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Functional Description The Raven control logic is subdivided into the following functions: PCI slave, PCI master, MPC slave and MPC master. The Raven data path logic is subdivided into the following functions: Data Path ‘A’ FIFOs/muxes, Data Path ‘B’...
Page 77: Figure 2-2. Mpc To Pci Address Decoding
For each map, there is an associated set of attributes. These attributes are used to enable read accesses, enable write accesses, enable write posting, and define the PCI transfer characteristics. http://www.motorola.com/computer/literature...
Page 78: Mpc Slave
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Each map decoder also includes a programmable 16-bit address offset. The offset is added to the 16 most significant bits of the MPC address, and the result is used as the PCI address. This offset allows PCI devices to reside at any PCI address, independent of the MPC address map.
Page 79: Table 2-1. Mpc Slave Response Command Types
Write Read 01010 Read Read-with-intent-to-modify 01110 Read Write-with-flush-atomic 10010 Write Reserved 10110 No Response Read-atomic 11010 Read Read-with-intent-to-modify-atomic 11110 Read Reserved 00011 No Response Reserved 00111 No Response Read-with-no-intent-to-cache 01011 Read Reserved 01111 No Response Reserved 1xx11 No Response http://www.motorola.com/computer/literature...
Page 80: Mpc Write Posting
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip MPC Write Posting The MPC write FIFO stores up to eight data beats in any combination of single- and four-beat (burst) transactions. If write posting is enabled, Raven stores the data necessary to complete an MPC write transfer to the PCI bus and immediately acknowledges the transaction on the MPC bus.
Page 81: Table 2-2. Mpc Transfer Types
Invalidate The MPC master incorporates an optional operating mode called Bus Hog. When Bus Hog is enabled, the MPC master will continually request the MPC bus for the entire duration of each PCI transfer. When Bus Hog is not http://www.motorola.com/computer/literature...
Page 82: Mpc Arbiter
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip enabled, the MPC master will structure its bus request actions according to the requirements of the FIFO. Caution should be exercised when using this mode since the over-generosity of bus ownership to the MPC master can be detrimental to the host CPU’s performance.
Page 83: Pci Address Mapping
MPC bus. An example of this is shown in Figure 2-4. http://www.motorola.com/computer/literature 2-11...
Page 84: Figure 2-4. Pci To Mpc Address Decoding
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip PCI Bus Address 8 0 8 0 1 2 3 4 Decode is >= <= PSADDx Register 7 0 8 0 9 0 0 0 Figure 2-4. PCI to MPC Address Decoding There are no limits imposed by Raven on how large of an address space a map decoder can represent.
Page 85: Figure 2-5. Pci To Mpc Address Translation
The decoders are prioritized as shown below. Decoder Priority PCI Slave 0 highest PCI Slave 1 PCI Slave 2 PCI Slave 3 lowest http://www.motorola.com/computer/literature 2-13...
Page 86: Pci Slave
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip RavenMPIC Control Registers: The RavenMPIC control registers are located within either PCI Memory or PCI I/O space using traditional PCI defined base registers within the predefined 64-byte header. Please see Raven Interrupt Controller Implementation on page 2-59 for more information.
Page 87: Table 2-3. Pci Slave Response Command Types
During I/O read cycles, the slave will perform integrity checking of the byte enables against the address being presented and assert SERR* in the event there is an error. http://www.motorola.com/computer/literature 2-15...
Page 88 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip The slave will only honor the Linear Incrementing addressing mode. The slave will perform a disconnect with data if any other mode of addressing is attempted. Device Selection: The PCI slave will always respond valid decoded cycles as a medium responder.
Page 89: Pci Write Posting
64-bit mode if the PCI bus has 64-bit mode enabled. If at any time during the transaction the PCI target indicates it can not support 64-bit mode, the PCI master will continue to transfer the remaining data in 32-bit mode. http://www.motorola.com/computer/literature 2-17...
Page 90: Table 2-4. Pci Master Command Codes
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip The PCI master can support Critical Word First (CWF) burst transfers. The PCI master will divide this transaction into two parts. The first part will start on the address presented with the CWF transfer request and continue up to the end of the current cache line.
Page 91 If the PCI master detects a target abort during a write, any untransferred portions of data will be dropped. The same rule applies if the PCI master generates a Master Abort cycle. http://www.motorola.com/computer/literature 2-19...
Page 92: Generating Pci Cycles
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Arbitration: The PCI master can support parking on the PCI bus. If the PCI master starts a transaction that is going to take more than one beat, the PCI master will continuously assert its request until the transaction has completed.
Page 93 The Raven will perform spread I/O addressing when the MEM bit is clear and the IOM bit is set. The Raven will take the MPC address, apply the offset specified in the MSOFFx register, and map the result to PCI as shown in Figure 2-6. http://www.motorola.com/computer/literature 2-21...
Page 94: Figure 2-6. Pci Spread I/O Address Translation
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip MPC Address + Offset 12 11 25 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCI Address 1915 9702 Figure 2-6. PCI Spread I/O Address Translation Spread I/O addressing allows each PCI device’s I/O registers to reside on a different MPC memory page, so device drivers can be protected from each other using memory page protection.
Page 95 IDSEL lines. During the address phase of a configuration cycle, only one of the upper address bits will be set. The device that has its IDSEL connected to the address bit being asserted will be selected for a http://www.motorola.com/computer/literature 2-23...
Page 96 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip configuration cycle. Raven decodes the Device Number to determine which of the upper address lines to assert. The decoding of the five-bit Device Number is show as follows: Device Number Address Bit 00000 AD31 00001 - 01010...
Page 97: Endian Conversion
PCI bus must be swapped such that the PCI bus looks big-endian from the MPC bus’s perspective. This association is true regardless of whether the transaction originates on the PCI bus or the MPC bus. This is shown in Figure 2-7. http://www.motorola.com/computer/literature 2-25...
Page 98: When Mpc Devices Are Little-Endian
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip PPC Bus 64-bit PCI PPC Bus 32-bit PCI 1916 9610 Figure 2-7. Big to Little-Endian Data Swap When MPC Devices are Little-Endian When all MPC devices are operating in little-endian mode, the originating address is modified to remove the exclusive-ORing applied by MPC60x processors before being passed on to the PCI bus.
Page 99: Raven Registers
This means that the processor’s internal view of the MPC registers will appear different depending on which mode the processor is operating in. With respect to the PCI bus, the RavenMPIC registers and the configuration registers are always represented in little-endian mode. http://www.motorola.com/computer/literature 2-27...
Page 100: Error Handling
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip The CONFIG_ADDRESS and CONFIG_DATA registers are actually represented in PCI space to the processor and are subject to the endian functions. For example, the powerup location of the CONFIG_ADDRESS register with respect to the MPC bus is $80000cf8 when Raven is in big- endian mode.
Page 101: Transaction Ordering
MPC bus in the following manner: Write posted transactions originating from the processor bus are flushed by the nature of the FIFO architecture. The Raven will hold the processor with wait states until the PCI bound FIFO is empty. http://www.motorola.com/computer/literature 2-29...
Page 102: Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Write posted transactions originated from the PCI bus are flushed whenever the PCI slave has accepted a write-posted transaction and the transaction has not completed on the MPC bus. Registers This chapter provides a detailed description of all Raven registers. These registers are broken into two groups: the MPC Registers and the PCI Configuration Registers.
Page 103 MEREN $FEFF0024 MERST $FEFF0028 MERAD $FEFF002C MERAT $FEFF0030 PIACK $FEFF0034 $FEFF0038 $FEFF003C $FEFF0040 MSADD0 $FEFF0044 MSOFF0 MSATT0 $FEFF0048 MSADD1 $FEFF004C MSOFF1 MSATT1 $FEFF0050 MSADD2 $FEFF0054 MSOFF2 MSATT2 $FEFF0058 MSADD3 $FEFF005C MSOFF3 MSATT3 $FEFF0060 $FEFF0064 $FFEF0068 $FEFF006C $FEFF0070 GPREG0(Upper) http://www.motorola.com/computer/literature 2-31...
Page 104: Vendor Id/Device Id Registers
$4801 VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PCI Configuration Registers. DEVID Device ID. This register identifies this particular device.
Page 105: Revision Id Register
When MPC Devices are Little-Endian on page 2-26. When LEND is clear, the MPC bus is operating in big-endian mode, and all data to/from PCI is swapped as described in When MPC Devices are Big-Endian on page 2-25. http://www.motorola.com/computer/literature 2-33...
Page 106 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip FLBRD Flush Before Read. If set, the Raven will guarantee that all PCI initiated posted write transactions will be completed before any MPC initiated read transactions will be allowed to complete. When FLBRD is clear, there will be no correlation between these transaction types and their order of completion.
Page 107: Mpc Arbiter Control Register
RESET*. This register may be used to report hardware configuration parameters to system software. MPC Arbiter Control Register Address $FEFF000C 0 1 2 3 4 5 6 7 8 9 Name MARB Operation Reset This register is not used by the MVME3600/4600. http://www.motorola.com/computer/literature 2-35...
Page 108: Prescaler Adjust Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Prescaler Adjust Register Address $FEFF0010 0 1 2 3 4 5 6 7 8 9 Name PADJ Operation Reset PADJ Prescaler Adjust. This register is used to specify a scale factor for the prescaler to ensure that the time base for the bus timer is 1 MHz.
Page 109 Enable. When this bit is set, the RTA bit in the MERST register will be used to assert the MCHK output to the bus master which initiated the transaction. When this bit is clear, MCHK will not be asserted. http://www.motorola.com/computer/literature 2-37...
Page 110 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip MATOI MPC Address Bus Time-out Interrupt Enable. When this bit is set, the MATO bit in the MERST register will be used to assert an interrupt through the OpenPIC interrupt controller. When this bit is clear, no interrupt will be asserted.
Page 111: Mpc Error Status Register
MEREN register is set, the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the MERAT register. When the PERRI bit in the MEREN register is set, the assertion of this bit will assert an interrupt through the OpenPIC interrupt controller. http://www.motorola.com/computer/literature 2-39...
Page 112 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip SERR PCI System Error. This bit is set when the PCI SERR* pin is asserted. It may be cleared by writing a 1 to it; writing a 0 to it has no effect. When the SERRM bit in the MEREN register is set, the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the MERAT register.
Page 113: Mpc Error Address Register
If the PERR or SERR bits are set in the MERST register, the contents of the MERAT register are zero. If the MATO bit is set the register is defined by the following figure: Address $FEFF002C 0 1 2 3 4 5 6 7 8 9 Name MERAT Operation Reset http://www.motorola.com/computer/literature 2-41...
Page 114 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip MIDx MPC Master ID. This field contains the ID of the MPC master which originated the transfer in which the error occurred. The encoding scheme is identical to that used in the GCSR register.
Page 115: Pci Interrupt Acknowledge Register
PCI bus as read data. MPC Slave Address (0,1 and 2) Registers Address MSADD0 - $FEFF0040 MSADD1 - $FEFF0048 MSADD2 - $FEFF0050 0 1 2 3 4 5 6 7 8 9 Name MSADDx START Operation Reset $0000 $0000 http://www.motorola.com/computer/literature 2-43...
Page 116: Mpc Slave Address (3) Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip To initiate a PCI cycle from the MPC bus, the MPC address must be greater than or equal to the START field and less than or equal to the END field. START Start Address.
Page 117: Mpc Slave Offset/Attribute (0,1 And 2) Registers
PCI address used for transfers from the MPC bus to PCI. This offset allows PCI resources to reside at addresses that would not normally be visible from the MPC bus. Read Enable. If set, the corresponding MPC slave is enabled for read transactions. http://www.motorola.com/computer/literature 2-45...
Page 118: Mpc Slave Offset/Attribute (3) Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Write Enable. If set, the corresponding MPC slave is enabled for write transactions. WPEN Write Post Enable. If set, write posting is enabled for the corresponding MPC slave. PCI Memory Cycle. If set, the corresponding MPC slave will generate transfers to or from PCI memory space.
Page 119: General Purpose Registers
The PCI Configuration Registers are compliant with the configuration register set described in the PCI Local Bus Specification, Revision 2.0. The CONFIG_ADDRESS and CONFIG_DATA registers described in this section are accessed from the MPC bus within PCI I/O space. http://www.motorola.com/computer/literature 2-47...
Page 120: Table 2-7. Raven Pci Configuration Register Map
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip All write operations to reserved registers will be treated as no-ops. That is, the access will be completed normally on the bus and the data will be discarded. Read accesses to reserved or unimplemented registers will be completed normally and a data value of 0 returned.
Page 121: Table 2-8. Raven Pci I/O Register Map
VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the MPC Registers. DEVID Device ID. This register identifies the particular device.
Page 122: Pci Command/ Status Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip PCI Command/ Status Registers Offset 0 9 8 7 6 5 4 3 2 1 0 Name PSTAT PCOMM Operation Reset IOSP IO Space Enable. If set, the Raven will respond to PCI I/O accesses when appropriate.
Page 123 Detected Parity Error. This bit is set whenever the Raven detects a parity error, even if parity error checking is disabled (see bit PERR in the PCI Command Register). It is cleared by writing it to 1; writing a 0 has no effect. http://www.motorola.com/computer/literature 2-51...
Page 124: Revision Id/ Class Code Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Revision ID/ Class Code Registers Offset 0 9 8 7 6 5 4 3 2 1 0 Name CLASS REVID Operation Reset $060000 REVID Revision ID. This register identifies the Raven revision level.
Page 125: Memory Base Register
Memory Type. These bits are hard-wired to zero to indicate that the RavenMPIC registers can be located anywhere in the 32-bit address space. Prefetch. This bit is hard-wired to zero to indicate that the RavenMPIC registers are not prefetchable. http://www.motorola.com/computer/literature 2-53...
Page 126: Pci Slave Address (0,1,2 And 3) Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip MEMBA Memory Base Address. These bits define the memory space base address of the RavenMPIC control registers. The MBASE decoder is disabled when the MBASE value is zero. PCI Slave Address (0,1,2 and 3) Registers Offset PSADD0 - $80 PSADD1 - $88...
Page 127: Pci Slave Attribute/ Offset (0,1,2 And 3) Registers
16 bits of the PCI address to determine the MPC address used for transfers from PCI to the MPC bus. This offset allows MPC resources to reside at addresses that would not normally be visible from PCI. http://www.motorola.com/computer/literature 2-55...
Page 128: Config_Address Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip CONFIG_ADDRESS Register The description of the CONFIG_ADDRESS register is presented in three perspectives: from the PCI bus, from the MPC Bus in big-endian mode, and from the MPC bus in little-endian mode. Note that the view from the PCI bus is purely conceptual, since there is no way to access the CONFIG_ADDRESS register from the PCI bus.
Page 129 CONFIG_DATA will be passed though as I/O Cycles. Special Cycles: Writing a one to this bit enables CONFIG_DATA to Special Cycle translation. If this bit is a zero, subsequent accesses to CONFIG_DATA will be passed though as I/O Cycles. http://www.motorola.com/computer/literature 2-57...
Page 130: Config_Data Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip CONFIG_DATA Register The description of the CONFIG_DATA register is also presented in three perspectives; from the PCI bus, from the MPC Bus in big-endian mode, and from the MPC bus in little-endian mode. Note that the view from the PCI bus is purely conceptual, since there is no way to access the CONFIG_DATA register from the PCI bus.
Page 131: Raven Interrupt Controller Implementation
The RavenMPIC receives interrupt inputs from 16 external sources, four interprocessor sources, four timer sources, and one Raven internal error detection source. The externally sourced interrupts 1 through 15 have two http://www.motorola.com/computer/literature 2-59...
Page 132: Csr's Readability
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip modes of activation; low level or active high positive edge. External interrupt 0 can be either level or edge activated with either polarity. The Interprocessor and timers interrupts are event activated. CSR’s Readability Unless explicitly specified, all registers are readable and return the last value written.
Page 133: Spurious Vector Generation
0. If the pass-through mode is disabled, the 8259 interrupts are delivered using the priority and distribution mechanisms of the RavenMPIC. The RavenMPIC does not interact with the vector fetch from the 8259 interrupt controller. http://www.motorola.com/computer/literature 2-61...
Page 134: Raven-Detected Errors
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Raven-Detected Errors Raven-detected errors are grouped together and sent to the interrupt logic as a singular interrupt source. The interrupt delivery mode for this interrupt is distributed. The Raven Error Vector-Priority Register should be programed for high true level sensitive activation.
Page 135 Note Because a deadlock condition can occur when the task register priorities for each processor are the same and both processors are targeted for interrupt delivery, the interrupt will be delivered to processor 0. http://www.motorola.com/computer/literature 2-63...
Page 136: Figure 2-8. Ravenmpic Block Diagram
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Block Diagram Description The description of the block diagram focuses on the theory of operation for the interrupt delivery logic. If the preceding section is a satisfactory description of the interrupt delivery modes and the reader is not interested in the logic implementation, this section can be skipped.
Page 137: Program Visible Registers
The IS will resolve an interrupt request in two Raven clock ticks. The IS also receives a second set of inputs from the ISR. During the End Of Interrupt cycle, these inputs are used to select which bits are to be cleared in the ISR. http://www.motorola.com/computer/literature 2-65...
Page 138: Interrupt Request Register (Irr)
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Interrupt Request Register (IRR) There is an Interrupt Request Register (IRR) for each processor. The IRR always passes the output of the IS except during Interrupt Acknowledge cycles. This guarantees that the vector which is read from the Interrupt Acknowledge Register is not changing due to the arrival of a higher priority interrupt.
Page 139 The contents of Task Register_0 is less than the contents of Task Register_1. Set3 The source ID in IRR_0 is from an internal source. The priority from IRR_0 is greater than the highest priority in ISR_0. The priority from IRR_0 is greater than the Task Register_0 contents. http://www.motorola.com/computer/literature 2-67...
Page 140: Mpic Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip There is a possibility for a priority tie between the two processors when resolving external interrupts. In that case the interrupt is always delivered to processor 0. This case is not defined in the above rule set. MPIC Registers The following conventions are used in the Raven register charts: Read Only field.
Page 141: Table 2-9. Ravenmpic Register Map
TIMER 3 BASE COUNT REGISTER $011d0 TIMER 3 VECTOR-PRIORITY REGISTER $011e0 TIMER 3 DESTINATION REGISTER $011f0 INT. SRC. 0 VECTOR-PRIORITY REGISTER $10000 INT. SRC. 0 DESTINATION REGISTER $10010 INT. SRC. 1 VECTOR-PRIORITY REGISTER $10020 INT. SRC. 1 DESTINATION REGISTER $10030 http://www.motorola.com/computer/literature 2-69...
Page 142 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Table 2-9. RavenMPIC Register Map (Continued) 0 9 8 7 6 5 4 3 2 1 0 INT. SRC. 2 VECTOR-PRIORITY REGISTER $10040 INT. SRC. 2 DESTINATION REGISTER $10050 INT. SRC. 3 VECTOR-PRIORITY REGISTER $10060 INT.
Page 143 IPI 0 DISPATCH REGISTER PROC. 1 $21040 IPI 1 DISPATCH REGISTER PROC. 1 $21050 IPI 2 DISPATCH REGISTER PROC. 1 $21060 IPI 3 DISPATCH REGISTER PROC. 1 $21070 CURRENT TASK PRIORITY REGISTER PROC. 1 $21080 IACK REGISTER $210a0 EOI REGISTER P1 $210b0 http://www.motorola.com/computer/literature 2-71...
Page 144: Feature Reporting Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Feature Reporting Register Offset $01000 0 9 8 7 6 5 4 3 2 1 0 Name FEATURE REPORTING NIRQ NCPU Operation Reset $00F NIRQ NUMBER OF IRQs. The number of the highest external IRQ source supported.
Page 145: Global Configuration Register
In the mixed mode, 8259 interrupts are delivered using the priority and distribution mechanism of RavenMPIC. The Vector/Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources. http://www.motorola.com/computer/literature 2-73...
Page 146: Vendor Identification Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Vendor Identification Register Offset $01080 0 9 8 7 6 5 4 3 2 1 0 Name VENDOR IDENTIFICATION Operation Reset There are two fields in the Vendor Identification Register which are not defined for the RavenMPIC implementation but are defined in the MPIC specification.
Page 147: Ipi Vector/Priority Registers
Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-75...
Page 148: Spurious Vector Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip Spurious Vector Register Offset $010E0 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation Reset VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch. Timer Frequency Register Offset $010F0...
Page 149: Timer Current Count Registers
0 9 8 7 6 5 4 3 2 1 0 Name TIMER BASECOUNT Operation Reset $00000000 COUNT INHIBIT. Setting this bit to one inhibits counting for this timer. Setting this bit to zero allows counting to proceed. http://www.motorola.com/computer/literature 2-77...
Page 150: Timer Vector/Priority Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip BASE COUNT. This field contains the 31 bit count for this timer. When a value is written into this register and the CI bit transitions from a 1 to a 0, it is copied into the corresponding Current Count register and the toggle bit in the Current Count register is cleared.
Page 151: Timer Destination Registers
External Source Vector/Priority Registers Offset Int Src 0 - $10000 Int Src 2 -> Int Src15 - $10020 -> $101E0 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE VECTOR/PRIORITY PRIOR VECTOR Operation Reset $000 http://www.motorola.com/computer/literature 2-79...
Page 152 Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip MASK MASK. Setting this bit disables any further interrupts from this source. If the mask bit is cleared while the bit associated with this interrupt is set in the IPR, the interrupt request will be generated.
Page 153: External Source Destination Registers
Reset $000 MASK MASK. Setting this bit disables any further interrupts from this source. If the mask bit is cleared while the bit associated with this interrupt is set in the IPR, the interrupt request will be generated. http://www.motorola.com/computer/literature 2-81...
Page 154: Raven-Detected Errors Destination Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip ACTIVITY. The activity bit indicates that an interrupt has been requested or that it is in-service. The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In-Service Register is set.
Page 155: Interprocessor Interrupt Dispatch Registers
PROCESSOR 1. The interrupt is directed to processor 1. PROCESSOR 0. The interrupt is directed to processor 0. Interrupt Task Priority Registers Offset Processor 0 $20080 Processor 1 $21080 0 9 8 7 6 5 4 3 2 1 0 Name INTERRUPT TASK PRIORITY Operation Reset http://www.motorola.com/computer/literature 2-83...
Page 156: Interrupt Acknowledge Registers
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip There is one Task Priority Register per processor. Priority levels from 0 (lowest) to 15 (highest) are supported. Setting the Task Priority Register to 15 masks all interrupts to this processor. Hardware will set the task register to $F when it is reset or when the Init bit associated with this processor is written to a one.
Page 157: End-Of-Interrupt Registers
3. The external interrupt handler calculates the address of the Interrupt Acknowledge register for this processor (RavenMPIC Base Address + 0x200A00 + (processor ID shifted left 12 bits)). 4. The external interrupt handler issues an Interrupt Acknowledge request to read the interrupt vector from the RavenMPIC. If the http://www.motorola.com/computer/literature 2-85...
Page 158: Reset State
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip interrupt vector indicates the interrupt source is the 8259, the interrupt handler issues a second Interrupt Acknowledge request to read the interrupt vector from the 8259. The RavenMPIC does not interact with the vector fetch from the 8259. 5.
Page 159: Operation
1. Mask the source using the MASK bit in the vector/priority register. 2. Wait for the activity bit (ACT) for that source to be cleared. 3. Make the desired changes. http://www.motorola.com/computer/literature 2-87...
Page 160: Eoi Register
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip 4. Unmask the source. This sequence ensures that the vector, priority, destination, and mask information remain valid until all processing of pending interrupts is complete. EOI Register Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event.
Page 161: Architectural Notes
Only when the task priority register is integrated within the processor, (such that it can be accessed as quickly as the MSRee bit defined in Programming Notes on page 2-85, for example), should the architecture require the task priority register to be updated synchronously with instruction execution. http://www.motorola.com/computer/literature 2-89...
Page 163: Introduction
3Falcon ECC Memory Controller Chipset Introduction This chapter provides a functional description and programming model for the Falcon. Most of the information for using the device in a system, programming it in a system, and testing it is contained here. The Falcon DRAM controller ASIC is designed for the MVME3600 and MVME4600 families of boards.
Page 164: Block Diagrams
Falcon ECC Memory Controller Chipset Function Features Error Notification for Software programmable Interrupt on Single/Double-Bit DRAM Error Error address and Syndrome Log Registers for Error Logging Does not provide TEA_ on Double-Bit Error. (Chip has no TEA_ pin.) ROM/Flash Interface Two blocks with each block being 16 bits wide (8 bits per Falcon), or 64 bits wide (32 bits per Falcon).
Page 165: Figure 3-1. Falcon Pair Used With Dram In A System
DRAM Address & ARRAYS Control Upper DRAM Data (64 Bits) Data Upper DRAM Address & Control Upper PowerPC Data (32 Bits) Check Upper DRAM Check-bits (8 Bits) 1900 9609 Figure 3-1. Falcon Pair Used with DRAM in a System http://www.motorola.com/computer/literature...
Page 166: Figure 3-2. Falcon Internal Data Paths (Simplified)
Falcon ECC Memory Controller Chipset PowerPC DRAM Side Side (64 Bits) Latched D (64 Bits) (64 Bits) (8 Bits) (8 Bits) (8 Bits) Uncorrected Data (64 Bits) 1901 9609 Figure 3-2. Falcon Internal Data Paths (Simplified) Computer Group Literature Center Web Site...
Page 167: Figure 3-3. Overall Dram Connections
BLOCK B BLOCK C BLOCK D LOWER LOWER LOWER LOWER BD_RAS_/CAS_ AC_RAS_/CAS_ RA/OE_/WE_ UPPER FALCON RD0-63 CKD0-7 DRAM DRAM DRAM DRAM BLOCK A BLOCK B BLOCK C BLOCK D UPPER UPPER UPPER UPPER 1902 9609 Figure 3-3. Overall DRAM Connections http://www.motorola.com/computer/literature...
Page 168: Functional Description
Falcon ECC Memory Controller Chipset Functional Description The following sections describe the logical function of the ASIC. The Falcon is designed to be used as a set of two chips. A pair of Falcons works with x1 or wider DRAM memory devices to form a memory system for the PowerPC 60x bus.
Page 169: Single-Beat Reads/Writes
70ns DRAMs it assumes that the devices are Page parts. When the pair is configured for 60ns DRAMs, it allows the devices to be either Page or Hyper-Page parts. Performance summaries using the different devices are shown in Table 3-1, Table 3-2, and Table 3-3. http://www.motorola.com/computer/literature...
Page 170: Table 3-1. Powerpc 60X Bus To Dram Access Timing When Configured For 70Ns
Falcon ECC Memory Controller Chipset Table 3-1. PowerPC 60 x Bus to DRAM Access Timing when Configured for 70ns Page Devices CLOCK PERIODS REQUIRED FOR: ACCESS TYPE Total Clocks Beat Beat Beat Beat 4-Beat Read after Idle (Quad- word aligned) 4-Beat Read after Idle (Quad- word misaligned) 4-Beat Read after 4-Beat Read...
Page 171: Table 3-2. Powerpc 60X Bus To Dram Access Timing When Configured For 60Ns
TS_ occurring at the minimum time after AACK_ is asserted. Also the two numbers shown in the 1st beat column are for page miss/page hit. 2. In some cases, the numbers shown are averages and specific instances may be longer or shorter. http://www.motorola.com/computer/literature...
Page 172: Table 3-3. Powerpc 60X Bus To Dram Access Timing When Configured For 50Ns Hyper Devices
Falcon ECC Memory Controller Chipset Table 3-3. PowerPC 60 x Bus to DRAM Access Timing when Configured for 50ns Hyper Devices CLOCK PERIODS REQUIRED FOR: ACCESS TYPE Total Clocks Beat Beat Beat Beat 4-Beat Read after Idle (Quad- word aligned) 4-Beat Read after Idle (Quad- word misaligned) 4-Beat Read after 4-Beat Read...
Page 173: Table 3-4. Powerpc 60X Bus To Rom/Flash Access Timing When Configured For 64 Bits (32 Bits Per Falcon)
Table 3-5. PowerPC 60 x Bus to ROM/Flash Access Timing when Configured for 16 Bits (8 Bits per Falcon) CLOCK PERIODS REQUIRED FOR: ACCESS TYPE Total Clocks Beat Beat Beat Beat 4-Beat Read 4-Beat Write 1-Beat Read (2 bytes to 8 bytes) 1-Beat Read (1 byte) 1-Beat Write http://www.motorola.com/computer/literature 3-11...
Page 174: Powerpc 60X Bus Interface
Falcon ECC Memory Controller Chipset PowerPC 60 x Bus Interface The Falcon pair has a PowerPC slave interface only. It has no PowerPC master interface. The slave interface is the mechanism for all accesses to DRAM, ROM/Flash, and Falcon registers/SRAM. Responding to Address Transfers When the Falcon pair detects an address transfer that it is to respond to, it asserts AACK_ immediately if there is no uncompleted PowerPC 60x bus...
Page 175: Cache Coherency Restrictions
144 bits back to DRAM. Error Reporting The Falcon pair checks data from the DRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-6 shows the actions it takes for different errors during these accesses. http://www.motorola.com/computer/literature 3-13...
Page 176: Table 3-6. Error Reporting
Falcon ECC Memory Controller Chipset Note that the Falcon pair does not assert TEA_ on double-bit errors. In fact, the Falcon pair does not have a TEA_ signal pin and it assumes that the system does not implement TEA_. The Falcon can, however, assert machine check (MCP_) on double-bit error.
Page 177: Error Logging
$FFF00000 - $FFFFFFFF. The overall enable and write enable bits are always cleared at reset. The reset vector enable bit is cleared or set at reset depending on external jumper configuration. This allows the board http://www.motorola.com/computer/literature 3-15...
Page 178 Falcon ECC Memory Controller Chipset designer to use external jumpers to enable/disable Block A/B ROM/Flash as the source of reset vectors. 2. The base address for each block is software programmable. At reset, Block A’s base address is $FF000000 and Block B’s base address is $FF800000.
Page 179: Table 3-7. Powerpc 60X To Rom/Flash Address Mapping When Rom/Flash
$000004 Upper $XX000009 $000005 Upper $XX00000A $000006 Upper $XX00000B $000007 Upper $XX00000C $000004 Lower $XX00000D $000005 Lower $XX00000E $000006 Lower $XX00000F $000007 Lower $XXFFFFF8 $7FFFFC Upper $XXFFFFF9 $7FFFFD Upper $XXFFFFFA $7FFFFE Upper $XXFFFFFB $7FFFFF Upper $XXFFFFFC $7FFFFC Lower http://www.motorola.com/computer/literature 3-17...
Page 180: Table 3-8. Powerpc 60X To Rom/Flash Address Mapping When Rom/Flash
Falcon ECC Memory Controller Chipset Table 3-7. PowerPC 60 x to ROM/Flash Address Mapping when ROM/Flash is 16 Bits Wide (8 Bits per Falcon) (Continued) PowerPC 60x A0-A31 ROM/Flash A22-A0 ROM/Flash Selected $XXFFFFFD $7FFFFD Lower $XXFFFFFE $7FFFFE Lower $XXFFFFFF $7FFFFF Lower Table 3-8.
Page 181: Refresh/Scrub
After each of the 4 cycles, the DRAM row address increments by one. When it reaches all 1’s, it rolls over and starts over at 0. Each time the row address rolls over, the block that is scrubbed toggles between A and B. http://www.motorola.com/computer/literature 3-19...
Page 182: Blocks A And/Or B Present, Blocks C And/Or D Present
Falcon ECC Memory Controller Chipset Every second time that the row address rolls over, which of the 4 cycles that is a scrub changes from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th, or from 4th to 1st. Every eighth time that the row address rolls over, the column address increments by one.
Page 183: Dram Arbitration
Each chip in the Falcon pair has an external register chip select pin which enables it to talk to an external set of registers. This interface is like the ROM/Flash interface but with less flexibility. It is intended for the system http://www.motorola.com/computer/literature 3-21...
Page 184: Csr Accesses
Falcon ECC Memory Controller Chipset designer to be able to implement general-purpose status/control signals with this external set. Refer to Programming Model for a description of this register set. CSR Accesses An important part of the operation of a Falcon pair is that the value written to the internal control registers and SRAM in each of the two chips must be the same at all times.
Page 185: Figure 3-4. Data Path For Reads From The Falcon Internal Csrs
Falcon. Internal register or test SRAM data written on the lower half of the data bus does not go to either Falcon in the pair, but the access is terminated normally with TA_. (See Figure 3-5.) http://www.motorola.com/computer/literature 3-23...
Page 186: Figure 3-5. Data Path For Writes To The Falcon Internal Csrs
Falcon ECC Memory Controller Chipset MPC60 x Master Upper FALCON Lower FALCON 1904 9609 Figure 3-5. Data Path for Writes to the Falcon Internal CSRs External register data that is written on the upper data bus goes through the upper Falcon, while data that is written on the lower data bus goes through the lower Falcon.
Page 187: Figure 3-6. Memory Map For Byte Reads To The Csr
Upper Falcon Upper Falcon $FEF80002 Upper Falcon $FEF80003 Lower Falcon $FEF80004 Lower Falcon $FEF80005 Lower Falcon $FEF80006 Lower Falcon $FEF80007 Upper Falcon $FEF80008 Upper Falcon $FEF80009 Lower Falcon $FEF807FF Figure 3-6. Memory Map for Byte Reads to the CSR http://www.motorola.com/computer/literature 3-25...
Page 188: Figure 3-7. Memory Map For Byte Writes To The Internal Register Set
Falcon ECC Memory Controller Chipset $FEF80000 Both Falcons Both Falcons $FEF80001 Both Falcons $FEF80002 Writes not allowed Here $FEF80003 Both Falcons $FEF80004 $FEF80005 $FEF80006 $FEF80007 Both Falcons $FEF80008 Both Falcons $FEF80009 $FEF807FF 1906 9609 Figure 3-7. Memory Map for Byte Writes to the Internal Register Set and Test SRAM 3-26 Computer Group Literature Center Web Site...
Page 189: Figure 3-8. Memory Map For 4-Byte Reads To The Csr
Figure 3-8. Memory Map for 4-Byte Reads to the CSR Writes not allowed Here $FEF80000 Both Falcons $FEF80004 Both Falcons $FEF80008 $FEF8000C $FEF807FC 1908 9609 Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set and Test SRAM http://www.motorola.com/computer/literature 3-27...
Page 190: Register Summary
Falcon ECC Memory Controller Chipset Register Summary Table 3-9 on the following page shows a summary of the CSR. Note that the table only shows addresses for accesses to the upper Falcon. To get the addresses for accesses to the lower Falcon, add 4 to the address shown. Since the only way to write to the lower Falcon’s internal register set and test SRAM is to duplicate what is written to the upper Falcon, only the addresses shown in the table should be used for writes to them.
Page 191: Table 3-9. Register Summary
FEF80050 ROM B BASE ROM B FEF80058 FEF80060 FEF80068 TEST PC TEST IR FEF80070 TEST A0 FEF80078 TEST A1 FEF80080 FEF80088 TEST D0 (Upper 8 Bits) FEF80090 TEST D0 (Middle 32 Bits) FEF80098 TEST D0 (Lower 32 Bits) http://www.motorola.com/computer/literature 3-29...
Page 192 Falcon ECC Memory Controller Chipset Table 3-9. Register Summary (Continued) FEF800A0 FEF800A8 TEST D1 (Upper 8 Bits) FEF800B0 TEST D1 (Middle 32 Bits) FEF800B8 TEST D1 (Lower 32 Bits) FEF800C0 FEF800C8 TEST D2 (Upper 8 Bits) FEF800D0 TEST D2 (Middle 32 Bits) FEF800D8 TEST D2 (Lower 32 Bits) FEF800E0...
Page 193: Detailed Register Bit Descriptions
The possible states of the bits after local and power-up reset are as defined below. The bit is affected by power-up reset (PURESET_). The bit is affected by local reset (HRESET_). The bit is not affected by reset. http://www.motorola.com/computer/literature 3-31...
Page 194: Vendor/Device Register
OPERATION RESET VENDID This read-only register contains the value $1507. It is the vendor number assigned to Motorola Inc. Note Note that the current value ($1507) of VENDID is not correct. The correct vendor ID should be $1057. This issue will be treated as just an erratum for now.
Page 195: Table 3-10. Ram Spd1,Ram Spd0 And Dram Type
DRAM timing used by the Falcon pair. They are encoded as shown: Table 3-10. ram spd1 , ram spd0 and DRAM Type ram spd0 , ram spd1 DRAM Speed DRAM Type 70ns Page Mode 60ns Page Mode Reserved 50ns http://www.motorola.com/computer/literature 3-33...
Page 196: Dram Attributes Register
Falcon ECC Memory Controller Chipset EDO refers to DRAMs that use an output latch on data. Sometimes these parts are referred to as Hyper-Page Mode DRAMs. To ensure reliable operation, the system should always be configured so that these two bits are encoded to match the slowest devices that are used.
Page 197: Table 3-11. Block_A/B/C/D Configurations
Table 3-11. Block_A/B/C/D Configurations ram a/b/c/d Block Devices Used Technology Comments siz0-2 SIZE %000 Block Not Present 1Mx4’s %001 16MB 1Mx18’s 16Mb 1Mx36’s 4Mb/1Mb SIMM/DIMM %010 32MB 2Mx8’s 16Mb 4Mx1’s 4Mx4’s 16Mb %011 64MB 4Mx18’s 64Mb 4Mx36’s 16Mb/4Mb SIMM/DIMM http://www.motorola.com/computer/literature 3-35...
Page 198: Dram Base Register
Falcon ECC Memory Controller Chipset Table 3-11. Block_A/B/C/D Configurations (Continued) ram a/b/c/d Block Devices Used Technology Comments siz0-2 SIZE %100 128MB 8Mx8’s 64Mb 16Mx1’s 16Mb %101 256MB 16Mx4’s 64Mb 16Mx36’s 64Mb/16Mb SIMM/DIMM %110 1024MB 64Mx1’s 64Mb %111 Reserved Note that it is important that all of the ram a/b/c/d siz0-2 bits be set to accurately match the actual size of their corresponding blocks.
Page 199: Clk Frequency Register
After power-up, this register is initialized to $42 (for 66MHz). por is set by the occurrence of power up reset. It is cleared by writing a one to it. Writing a 0 to it has no effect. http://www.motorola.com/computer/literature 3-37...
Page 200: Ecc Control Register
Falcon ECC Memory Controller Chipset ECC Control Register $FEF80028 ADDRESS NAME OPERATION READ ZERO RESET refdis When set, refdis causes the refresher and all of its associated counters and state machines to be cleared and maintained that way until refdis is removed (cleared). If a refresh cycle is in process when refdis is updated by a write to this register, the update does not take effect until the refresh cycle has completed.
Page 201 DRAM. If the location to which check- bits are being written has a single- or double-bit error, data in the location may be altered by the write check-bits operation. To avoid this, it is recommended that the derc http://www.motorola.com/computer/literature 3-39...
Page 202 Falcon ECC Memory Controller Chipset bit also be set while the rwcb bit is set. A possible sequence for performing read-write check-bits is as follows: 1. Disable scrub writes by clearing the swen bit if it is set. 2. Stop all DRAM Tester operations by clearing the trun bit. 3.
Page 203 The Falcon pair does not assert TEA as a result of a multiple bit error. In fact, the Falcon pair does not have a Caution TEA_ signal pin and it assumes that the system does not implement TEA_. http://www.motorola.com/computer/literature 3-41...
Page 204: Error Logger Register
Falcon ECC Memory Controller Chipset Error Logger Register $FEF80030 ADDRESS NAME ERROR_SYNDROME SBE_COUNT OPERATION READ ONLY READ/WRITE RESET The Error Logger and Error Address Registers behave the same as the other registers, in that data written to the upper Falcon is automatically duplicated in the lower Falcon.
Page 205 When all the bits are zero, there was no error. Note that if the logged error was non-correctable, then these bits are meaningless. Refer to ECC Codes on page 3-59 for a decoding of the syndromes. http://www.motorola.com/computer/literature 3-43...
Page 206: Error_Address Register
Falcon ECC Memory Controller Chipset esblk0,esblk1 Together these two bits indicate which block of DRAM was being accessed when their Falcon logged a scrub error. esblk0,esblk1 are 0,0 for Block A; 0,1 for Block B; 1,0 for Block C; and 1,1 for Block D. scof scof is set by its SBE COUNT register rolling over from $FF to $00.
Page 207: Table 3-12. Rtest Encodings
Test Mode selected %000 Normal Counter Operation %001 RA counts at 16x %010 RA counts at 256x %011 RA is always at roll value for CA %100 CA counts at 16x %101 CA counts at 256x %110 reserved %111 reserved http://www.motorola.com/computer/literature 3-45...
Page 208: Refresh/Scrub Address Register
Falcon ECC Memory Controller Chipset Refresh/Scrub Address Register $FEF80048 ADDRESS ROW ADDRESS COL ADDRESS NAME OPERATION READ/WRITE READ/WRITE RESET ROW ADDRESS These bits form the row address counter used by the refresher/scrubber for all blocks of DRAM. The row address counter increments by one after each refresh/scrub cycle.
Page 209: Rom A Base/Size Register
8 bits. When rom_a_64 is set, Block A is 64 bits wide, where each Falcon interfaces to 32 bits. rom_a_64 matches the value that was on the CKD2 pin at power-up reset. It cannot be changed by software. http://www.motorola.com/computer/literature 3-47...
Page 210: Table 3-13. Rom/Flash Block A Size Encoding
Falcon ECC Memory Controller Chipset rom a siz The rom a siz control bits are the size of ROM/Flash for Block A. They are encoded as shown below. Table 3-13. ROM/Flash Block A Size Encoding BLOCK rom a siz SIZE %000 %001 %010...
Page 211: Table 3-15. Read/Write To Rom/Flash
1-byte No Response write 4-byte Misaligned No Response write 4-byte Aligned Normal termination, but write 4-byte Aligned no write to ROM/Flash write 4-byte Aligned Normal termination, write occurs to ROM/Flash No Response write 2,3,5,6,7, 8,32-byte Normal Termination read http://www.motorola.com/computer/literature 3-49...
Page 212: Rom B Base/Size Register
Falcon ECC Memory Controller Chipset ROM B Base/Size Register $FEF80058 ADDRESS ROM B BASE NAME READ/WRITE OPERATION READ ZERO $FF4 PL RESET ROM B BASE These control bits define the base address for ROM/Flash Block B. ROM B BASE bits 0-11 correspond to PowerPC 60x address bits 0 - 11 respectively.
Page 213: Table 3-16. Rom/Flash Block B Size Encoding
When rom b en is cleared they are disabled. rom b we When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared they are disabled. Refer back to Table 3-15 on page 3-49 for more details. http://www.motorola.com/computer/literature 3-51...
Page 214: Dram Tester Control Registers And Test Sram
Falcon ECC Memory Controller Chipset DRAM Tester Control Registers and Test SRAM The tester should not be used by software. The trun and tsse bits (bits 0 and 1 of the register at address $FEF80060) should never be set. Caution 32-Bit Counter $FEF80100 ADDRESS...
Page 215: Power-Up Reset Status Register 1
Memory Configuration Register (MEMCR). Power-Up Reset Status Register 2 $FEF80500 ADDRESS NAME PR_STAT2 OPERATION READ RESET PR_STAT2 PR_STAT2 (power-up reset status) reflects the value that was on the RD32-RD63 signal pins at power-up reset. This register is read-only. http://www.motorola.com/computer/literature 3-53...
Page 216: External Register Set
Falcon, or to the lower Falcon. Note For descriptions of how these registers are used in the MVME3600 series and MVME4600 series boards, refer to the Falcon-Controlled System Registers in Chapter 1, especially the System External Cache Control Register (SXCCR)
Page 217: Software Considerations
Since software has no way of controlling refresh accesses to DRAM, the hardware is designed so that updating control bits coincidentally with refreshes is not a problem. An exception to this is the ROW_ADDRESS and COL_ADDRESS bits. It is not intended that software write to these bits anyway. http://www.motorola.com/computer/literature 3-55...
Page 218: Sizing Dram
Falcon ECC Memory Controller Chipset As with DRAM, software should not change control register bits that affect ROM/Flash while the affected Block is being accessed. This generally means that the ROM/Flash size, base address, enable, write enable, etc. are changed only while executing initially in the reset vector area ($FFF00000 - $FFFFFFFF).
Page 219 Sizing needs to continue for this block by programming its control bits to the next smaller size and repeating steps 4 and 5. 6. If no match is found for any size then the block is unpopulated and has a size of 0MB. http://www.motorola.com/computer/literature 3-57...
Page 220: Table 3-17. Sizing Addresses
Falcon ECC Memory Controller Chipset Each size that is checked has a specific set of locations that must be written and read. The following table shows the addresses that go with each size. Table 3-17. Sizing Addresses 1024MB 256MB 128MB 64MB 32MB 16MB...
Page 221: Table 3-18. Powerpc 60X Address To Dram Address Mappings
In order to relate this information to PowerPC addresses and bit numbers, the user needs to understand how the Falcon pair positions PowerPC data in DRAM. See Data Paths on page 3-62 for an explanation of this. http://www.motorola.com/computer/literature 3-59...
Page 222: Table 3-19. Syndrome Codes Ordered By Bit In Error
Falcon ECC Memory Controller Chipset Note that Table 3-19 Table 3-20 are the same whether the Falcon is configured as upper or as lower. Table 3-19. Syndrome Codes Ordered by Bit in Error Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome rd16 rd32 rd48...
Page 223: Table 3-20. Single-Bit Errors Ordered By Syndrome Code
3-61...
Page 224: Data Paths
Falcon ECC Memory Controller Chipset Data Paths Because of the Falcon “pair” architecture, data paths can be confusing. Figure 3-10 attempts to show the placement of data that is written by a PowerPC master to DRAM. Table 3-21 shows the same information in tabular format.
Page 225: Figure 3-10. Powerpc Data To Dram Data Correspondence
Data Paths rd63 rd32 Lower Falcon’s rd31 DRAM dl31 PowerPC Data dh31 rd63 Upper Falcon’s DRAM rd32 rd31 1909 9609 Figure 3-10. PowerPC Data to DRAM Data Correspondence http://www.motorola.com/computer/literature 3-63...
Page 226: Table 3-21. Powerpc Data To Dram Data Mapping
Falcon ECC Memory Controller Chipset Table 3-21. PowerPC Data to DRAM Data Mapping PowerPC DRAM Array Upper Falcon DRAM Lower Falcon DRAM A[27] A[28] Data Bits RA[12] Data Bits Data Bits dh[00:07] rd[00:07] dh[08:15] rd[08:15] dh[16:23] rd[16:23] dh[24:31] rd[24:31] dl[00:07] rd[00:07] dl[08:15] rd[08:15]...
Page 227: General Information
64-bit VMEbus to PCI interface in one device. Designed by Tundra Semiconductor Corporation in consultation with Motorola, the Universe is compliant with the VME64 specification and is tuned to the new generation of high speed processors. The Universe is ideally suited for CPU boards acting as both master and slave in the VMEbus system, and is particularly fitted for PCI local systems.
Page 228: Functional Description
Universe (VMEbus to PCI) Chip – D64 (MBLT)/D32/D16/D08 master and slave – BLT, ADOH, RMW, LOCK Automatic initialization for slave-only applications Flexible register set, programmable from both the PCI bus and VMEbus ports Full VMEbus system controller functionality IEEE 1149.1 JTAG testability support, and Available in 313-pin Plastic BGA and 324-pin contact Ceramic Functional Description Architectural Overview...
Page 229: Figure 4-1. Architectural Diagram For The Universe
FIFO prefetch read FIFO Master Slave coupled read PCI Bus Slave Channel posted writes FIFO VMEbus Slave Master coupled read logic Interrupt Channel Interrupt Handler Interrupts Interrupts Interrupter Register Channel 1894 9609 Figure 4-1. Architectural Diagram for the Universe http://www.motorola.com/computer/literature...
Page 230: Vmebus Interface
Universe (VMEbus to PCI) Chip VMEbus Interface Universe as VMEbus Slave The Universe VME Slave Channel accepts all of the addressing and data transfer modes documented in the VME64 specification (except A64 and those intended to support 3U applications, for example, A40 and MD32). Incoming write transactions from the VMEbus may be treated as either coupled or posted, depending upon the programming of the VMEbus slave image.
Page 231: Pci Bus Interface
The Universe becomes PCI master when the PCI Master Interface is internally requested by the VME Slave Channel or the DMA Channel. There are mechanisms provided which allow the user to configure the relative priority of the VME Slave Channel and the DMA Channel. http://www.motorola.com/computer/literature...
Page 232: Interrupter And Interrupt Handler
Universe (VMEbus to PCI) Chip Interrupter and Interrupt Handler Interrupter The Universe interrupt channel provides a flexible scheme to map interrupts to either the PCI bus or VMEbus interface. Interrupts are generated from either hardware or software sources (refer to Interrupter in the Universe User Manual for a full description of hardware and software sources).
Page 233: Dma Controller
Universe operational characteristics. The UCSRs are divided into three groups: PCI Configuration Space (PCICS) VMEbus Control and Status Registers (VCSR), and Universe Device Specific Status Registers (UDSR) The Universe registers are little-endian. http://www.motorola.com/computer/literature...
Page 234: Figure 4-2. Ucsr Access Mechanisms
Universe (VMEbus to PCI) Chip The figure below summarizes the supported register access mechanisms. VMEbus Configuration and Status Registers (VCSR) UNIVERSE DEVICE SPECIFIC REGISTERS 4 Kbytes (UDSR) PCI CONFIGURATION SPACE (PCICS) 1895 9609 Figure 4-2. UCSR Access Mechanisms Universe Register Map Table 4-1 below lists the Universe registers by address offset.
Page 235: Table 4-1. Universe Register Map
PCI Slave Image 0 Base Address Register LSI0_BS PCI Slave Image 0 Bound Address Register LSI0_BD PCI Slave Image 0 Translation Offset LSI0_TO Universe Reserved PCI Slave Image 1 Control LSI1_CTL PCI Slave Image 1 Base Address Register LSI1_BS http://www.motorola.com/computer/literature...
Page 236 Universe (VMEbus to PCI) Chip Table 4-1. Universe Register Map (Continued) Offset Register Name PCI Slave Image 1 Bound Address Register LSI1_BD PCI Slave Image 1 Translation Offset LSI1_TO Universe Reserved PCI Slave Image 2 Control LSI2_CTL PCI Slave Image 2 Base Address Register LSI2_BS PCI Slave Image 2 Bound Address Register LSI2_BD...
Page 237 340 - 3FC Universe Reserved Master Control MAST_CTL Miscellaneous Control MISC_CTL Miscellaneous Status MISC_STAT User AM Codes Register USER_AM 410 - EFC Universe Reserved VMEbus Slave Image 0 Control VSI0_CTL VMEbus Slave Image 0 Base Address Register VSI0_BS http://www.motorola.com/computer/literature 4-11...
Page 238 Universe (VMEbus to PCI) Chip Table 4-1. Universe Register Map (Continued) Offset Register Name VMEbus Slave Image 0 Bound Address Register VSI0_BD VMEbus Slave Image 0 Translation Offset VSI0_TO Universe Reserved VMEbus Slave Image 1 Control VSI1_CTL VMEbus Slave Image 1 Base Address Register VSI1_BS VMEbus Slave Image 1 Bound Address Register VSI1_BD...
Page 239: Universe Chip Problems After A Pci Reset
Universe Master Enable and Memory Enable in the PCI_CSR (Configuration Space register) are enabled, even before the PCI_BS register has been initialized. The symptoms can be alleviated by modifying the PCI probe list such that the Universe PCI configuration is done first. http://www.motorola.com/computer/literature 4-13...
Page 240 Universe (VMEbus to PCI) Chip The Configuration Space enables are not the only things enabled after a PCI reset. The LSI0 image may also not be disabled by a PCI reset, regardless of the enable bit’s Power Up condition. If the image is active at the time the reset occurs, it will remain enabled through the reset.
Page 241: Examples
Many of these customers replace Motorola’s firmware, or overwrite the firmware settings for the Universe chip. These customers may run into this problem. Customers should not encounter any problems if they leave Motorola’s PPCBug debugger intact. Examples Example 1: MVME2600 Series Board Exhibits Problem Use an MVME2600 series board to exhibit the problem.
Page 242 Universe (VMEbus to PCI) Chip With the LSI0 enabled, the registers are: 80821000 1012000 21012000 3efee000 2. Execute a bye command. 3. Manually enable access to the Universe register set, and read the LSI0 registers: 80820000 20000000 This means that the PCI reset changed the image as follows: from supervisor address modifier to user from PCI space base address 1012000 to 0 (size of 2000.0000 constant)
Page 243: Example 2: Mvme3600 Series Board Acts Differently
Universe Chip Problems after a PCI Reset Example 2: MVME3600 Series Board Acts Differently Repeat portions of the earlier example on an MVME3600 series board. This board had not previously been seen to hang upon PCI reset. This particular board had customized values for the LSI0 setup parameters.
Page 244 Universe (VMEbus to PCI) Chip 4. Now try modifying the LSI0 env parameters, to be the same as those on the MVME260x which failed: printenv vme3_lsi0_vmeaddr 1073741824 1073741824 vme3_lsi0_size 536870912 536870912 vme3_lsi0_phi After a power-up, before the init code ran, the LSI0 values are: 800000 0 0 0 5.
Page 245: Example 3: Universe Chip Is Checked At Tundra
The engineer at Tundra re-ran the simulation based on the information given him. He saw exactly what the Motorola engineers had seen, for example, that the LSI0_BS, LSI0_BD, and LSI0_TO values change, as well as the LSI0_CTL fields for program, super, and vct. He checked to see if this is in fact what the Universe is supposed to do.
Page 247: Table 5-1. Pci Arbitration Assignments
5Programming Details Introduction This chapter contains details of several programming functions that are not tied to any specific ASIC chip. PCI Arbitration PCI arbitration is performed by the PCI-to-ISA Bridge (PIB) which supports six PCI external PCI masters. The PIB can also be a PCI master for ISA DMA functions.
Page 248: Figure 5-1. Mvme3600/4600 Series Interrupt Architecture
Programming Details Interrupt Handling The interrupt architecture of the MVME3600/4600 series VME Processor Modules is shown in the following figure: INT_ Processor (8259 Pair) MCP_ RavenMPIC INT_ Processor SERR_& PERR_ PCI Interrupts MCP_ ISA Interrupts 11559.00 9609 Figure 5-1. MVME3600/4600 Series Interrupt Architecture Computer Group Literature Center Web Site...
Page 249: Table 5-2. Ravenmpic Interrupt Assignments
IRQ7 Level PCI-VME INT 2 (Universe LINT2#) IRQ8 Level PCI-VME INT 3 (Universe LINT3#) IRQ9 Level PCI-PMC1/PMC2 INTA# IRQ10 Level PCI-PMC1/PMC2 INTB# (Secondary Ethernet) IRQ11 Level PCI-PMC1/PMC2 INTC# (Secondary SCSI) IRQ12 Level PCI-PMC1/PMC2 INTD# IRQ13 Level LM/SIG Interrupt 0 http://www.motorola.com/computer/literature...
Page 250: Interrupts
Programming Details Table 5-2. RavenMPIC Interrupt Assignments (Continued) MPIC Edge/ Polarity Interrupt Source Notes Level IRQ14 Level LM/SIG Interrupt 1 IRQ15 Not used Notes 1. Interrupt from the PCI/ISA Bridge. 2. Interrupt from the Falcon chipset for a Single and/or Double bit memory error.
Page 251: Figure 5-2. Pib Interrupt Handler Block Diagram
PIRQ1_ IRQx IRQ7 PIRQ Route Control Register PIRQ2_ IRQx IRQ8 PIRQ Route Control Register IRQ9 IRQ10 IRQ11 Controller 2 PIRQ3_ IRQx (INT2) IRQ12 PIRQ Route Control Register IRQ13 IRQ14 IRQ15 1897 9609 Figure 5-2. PIB Interrupt Handler Block Diagram http://www.motorola.com/computer/literature...
Page 252: Table 5-3. Pib Pci/Isa Interrupt Assignments
Programming Details The assignments of the PCI and ISA interrupts supported by the PIB are as follows: Table 5-3. PIB PCI/ISA Interrupt Assignments Edge/ Interrupt Source Level IRQ0 INT1 Edge High Timer 1 / Counter 0 IRQ1 Edge High Keyboard 3-10 IRQ2 Edge High...
Page 253: Isa Dma Channels
6. The RavenMPIC, when present, should be used for these interrupts. 7. PMC Interrupt is the OR of INTA#, INTB#, INTC#, INTD#. ISA DMA Channels Refer to Chapter 1, Board Description and Memory Maps for information on the ISA DMA channels. http://www.motorola.com/computer/literature...
Page 254: Table 5-4. Reset Sources And Devices Affected
Programming Details Exceptions Sources of Reset There are eight potential sources of reset on the MVME3600/4600 series. They are: 1. Power-On Reset 2. RESET Switch 3. Watchdog Timer Reset via the MK48T59/559 Timekeeper device 4. Port 92 Register via the PIB 5.
Page 255: Soft Reset
Processor Init Register of the RavenMPIC appropriately. Universe Chip Problems after a PCI Reset Under certain conditions, there can be problems with the Universe chip after a PCI reset. Refer to Chapter 4, Universe (VMEbus to PCI) Chip the details. http://www.motorola.com/computer/literature...
Page 256: Table 5-5. Error Notification And Handling
Programming Details Error Notification and Handling The Raven and Falcon chipset can detect certain hardware errors and can be programmed to report these errors via the RavenMPIC interrupts or Machine Check Interrupt. Note that the TEA* signal is not used at all by the MVME3600/4600 series.
Page 257: Endian Issues
NT) and big-endian software (for example, AIX). Because the PowerPC processor is inherently big-endian, PCI is inherently little-endian, and the VMEbus is big-endian, things do get rather confusing. Figure 5-3 Figure 5-4 show how the MVME3600/4600 series handles the endian issue in big-endian and little-endian modes: http://www.motorola.com/computer/literature 5-11...
Page 258: Figure 5-3. Big-Endian Mode
Programming Details Big-Endian PROGRAM Falcons DRAM 60X System Bus Raven Big-Endian N-way Byte Swap Little-Endian PCI Local Bus Universe Little-Endian N-way Byte Swap Big-Endian VMEbus 1898 9609 Figure 5-3. Big-Endian Mode 5-12 Computer Group Literature Center Web Site...
Page 259: Figure 5-4. Little-Endian Mode
Endian Issues Little-Endian PROGRAM Little-Endian Big-Endian EA Modification (XOR) Falcons DRAM 60X System Bus Raven Big-Endian EA Modification Little-Endian PCI Local Bus Universe Little-Endian N-way Byte Swap Big Endian VMEbus 1899 9609 Figure 5-4. Little-Endian Mode http://www.motorola.com/computer/literature 5-13...
Page 260: Processor/Memory Domain
Programming Details Processor/Memory Domain The MPC604 processor can operate in both big-endian and little-endian mode. However, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. The MPC registers inside Raven, the registers inside the Falcon chipset, the DRAM, the ROM/Flash and the system registers always appear as big- endian.
Page 261: Pci-Ethernet
Raven. The result has the desirable effect of being transparent to the big-endian software. In little-endian mode, however, software must be aware of the byte- swapping effect from the Universe and the address reverse-rearranging effect of the Raven. http://www.motorola.com/computer/literature 5-15...
Page 262: Rom/Flash Initialization
Programming Details ROM/Flash Initialization There are two methods used to inject code into the Flash in Bank A: (1) In- circuit programming and (2) Loading code from the ROM/Flash Bank B. For the second method, the hardware must direct the Falcon chipset to map the FFF00000-FFFFFFFF address range to Bank B following a hard reset.
Page 263: Motorola Computer Group Documents
ARelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature...
Page 264: Manufacturers' Documents
Table A-2. Manufacturers’ Documents Document Title and Source Publication Number PowerPC 604 RISC Microprocessor User’s Manual MPC604EUM/AD Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 Web Site: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com IBM Microelectronics G522-0330-00 PowerPC604e User Manual Web Site: http://www.chips.ibm.com/techlib/products/powerpc/manuals...
Page 265 Z8536 CIO Counter/Timer and Parallel I/O Unit DM10001176 Product Specification and User’s Manual ® (in Z8000 Family of Products Data Book) Web Site: http://www.zilog.com/products/zx80dev.html#um W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB) W83C553F Winbond Electronics Corporation; Web Site: http://www.winbond.com.tw/product/ http://www.motorola.com/computer/literature...
Page 266: Related Specifications
Related Documentation Table A-2. Manufacturers’ Documents (Continued) Document Title and Source Publication Number Universe User Manual 8091042_MD300_ 05.pdf Tundra Semiconductor Corporation Web Site: http://www.tundra.com/page.cfm?tree_id=100008#Universe II (CA91C042) Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided.
Page 267 1.0, Volumes I and II; International Business Machines Corporation Web Site: http://www.ibm.com PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 Web Site: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com Morgan Kaufmann Publishers, Inc.
Page 269 Index Numerics blocks A and/or B present, blocks C and D not present 3-19 32-Bit Counter 3-52 blocks A and/or B present, blocks C and/or D 8259 compatibility 2-61 present 3-20 8259 interrupts bus interface (60x) 3-12 8259 mode 2-88 cache coherency 3-12 A0-A31...
Page 270 Index data path mapping 3-64 ERROR_ADDRESS 3-44 data paths 3-62 ERROR_SYNDROME 3-43 data transfers 3-12 esbt 3-43 default PCI memory map 1-14 escb 3-43 default processor memory map esen 3-43 derc 3-40 example 1 4-15 Disable Error Correction control bit 3-40 example 2 4-17...
Page 271 MPC to PCI address decoding ister 1-40 MPC to PCI address translation Location Monitor Upper Base Address Reg- MPC transfer types ister 1-40 MPC write posting MPIC registers 2-68 MVME3600 series manufacturers’ documents MVME3600 series system block diagram http://www.motorola.com/computer/literature IN-3...
Page 272 Index MVME3600/4600 series features summary PCI Slave Attribute/ Offset (0,1,2 and 3) Registers 2-55 MVME3600/4600 series interrupt architec- PCI slave response command types 2-15 ture PCI spread I/O address translation 2-22 MVME4600 series PCI to MPC address decoding 2-12 MVME4600 series system block diagram PCI to MPC address translation 2-13 MVME712M mode...
Page 273 2-68 rtest0-rtest2 3-45 Read/Write Checkbits control bit 3-38 rwcb 3-38 reads/writes to ROM/Flash 3-49 refdis 3-38 Refresh Counter Test control bits 3-45 SBE_COUNT 3-44 Refresh/Scrub 3-19 scb0,scb1 3-45 Refresh/Scrub Address Register 3-46 scien 3-41 register bit descriptions 3-31 http://www.motorola.com/computer/literature IN-5...
Page 274 Index scof 3-44 transaction ordering 2-29 Scrub Counter bits 3-45 trun bit 3-52 Scrub Write Enable control bit 3-45 tsse bit 3-52 Scrub/Refresh Register 3-45 Semaphore Register 1 1-41 UCSR access mechanisms Semaphore Register 2 1-41 Universe (VMEbus to PCI) chip Seven-Segment Display Register 1-36 Universe as PCI master...
Page 275 MPC devices are little endian 2-26 writing to the control registers 3-55 Z85230 ESCC and Z8536 CIO registers and port pins 1-43 Z8536 CIO port pins 1-44 Z8536 CIO port pins assignment 1-44 Z8536/Z85230 access registers 1-43 Z8536/Z85230 registers 1-43 http://www.motorola.com/computer/literature IN-7...

This manual is also suitable for:

Mvme4600 series

Motorola MVME3600 Series Programmer's Reference Manual

CHAPTER 1 Board Description and Memory Maps

CHAPTER 2 Raven PCI Host Bridge & Multi-Processor

CHAPTER 3 Falcon ECC Memory Controller Chipset

CHAPTER 4 Universe (Vmebus to PCI) Chip

CHAPTER 5 Programming Details

APPENDIX A Related Documentation

Quick Links

Related Manuals for Motorola MVME3600 Series

Summary of Contents for Motorola MVME3600 Series