Motorola HC12 Refrence Manual page 343

Table A-1 Instruction Set Summary (Continued)
Source
Form
BVC rel
Branch if Overflow Bit Clear (if V = 0)
BVS rel Branch if Overflow Bit Set (if V = 1)
(SP) – 2 ⇒ SP;
CALL opr , page
RTN :RTN
H
(SP) – 1 ⇒ SP;
(PPG) ⇒ M
pg ⇒ PPAGE register;
Program address ⇒ PC
Call subroutine in extended memory
(Program may be located on another
expansion memory page.)
CALL [D, r ] Indirect modes get program address
CALL [ opr , r ] and new pg value based on pointer.
r = X, Y, SP, or PC
CBA (A) – (B)
Compare 8-Bit Accumulators
0 ⇒ C
CLC
Translates to ANDCC #$FE
0 ⇒ I
CLI
Translates to ANDCC #$EF
(enables I-bit interrupts)
0 ⇒ M
CLR opr
0 ⇒ A
CLRA
0 ⇒ B
CLRB
0 ⇒ V
CLV
Translates to ANDCC #$FD
CMPA opr (A) – (M)
Compare Accumulator A with Memory
CMPB opr (B) – (M)
Compare Accumulator B with Memory
CPU12
REFERENCE MANUAL
Operation
⇒ M
:M
L (SP) (SP+1)
;
(SP)
Clear Memory Location
Clear Accumulator A
Clear Accumulator B
INSTRUCTION REFERENCE
Addr. Machine
Mode Coding (hex)
REL 28 rr 3/1
REL 29 rr 3/1
EXT 4A hh ll pg
IDX 4B xb pg
IDX1 4B xb ff pg
IDX2 4B xb ee ff pg
[D,IDX] 4B xb
[IDX2] 4B xb ee ff
INH 18 17
IMM 10 FE
IMM 10 EF
EXT 79 hh ll
IDX 69 xb
IDX1 69 xb ff
IDX2 69 xb ee ff
[D,IDX] 69 xb
[IDX2] 69 xb ee ff
INH 87
INH C7
IMM 10 FD
IMM 81 ii
DIR 91 dd
EXT B1 hh ll
IDX A1 xb
IDX1 A1 xb ff
IDX2 A1 xb ee ff
[D,IDX] A1 xb
[IDX2] A1 xb ee ff
IMM C1 ii
DIR D1 dd
EXT F1 hh ll
IDX E1 xb
IDX1 E1 xb ff
IDX2 E1 xb ee ff
[D,IDX] E1 xb
[IDX2] E1 xb ee ff
*
~
S X H I N Z V C
– – – – – – –
– – – – – – –
8 – – – – – – –
8
8
9
10 – – – – – – –
10
– – ∆ ∆ ∆
2 – –
1 – – – – – – –
1 – – – 0 – – –
3 – – – – 0 1 0
2
3
3
5
5
1
1
1 – – – – – – 0
– – ∆ ∆ ∆
1 – –
3
3
3
3
4
6
6
– – ∆ ∆ ∆
1 – –
3
3
3
3
4
6
6
MOTOROLA
–
–
–
–
∆
0
–
0
–
∆
∆
A-5