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O — Optional cycle. Program information is always fetched as aligned 16-bit words.
P — Program word access. Program information is fetched as aligned 16-bit words.
r — 8-bit data read. These cycles are stretched only when controlled by a chip-select
R — 16-bit data read. These cycles are extended to two bus cycles if the MCU is op-
s — Stack 8-bit data. These cycles are stretched only when controlled by a chip-se-
S — Stack 16-bit data. These cycles are extended to two bus cycles if the MCU is
w — 8-bit data write. These cycles are stretched only when controlled by a chip-se-
W — 16-bit data write. These cycles are extended to two bus cycles if the MCU is op-
u — Unstack 8-bit data. These cycles are stretched only when controlled by a chip-
MOTOROLA
6-6
When an instruction consists of an odd number of bytes, and the first byte is mis-
aligned, an O cycle is used to make an additional program word access (P) cycle
that maintains queue order. In all other cases, the O cycle appears as a free (f)
cycle. The $18 prebyte for page two opcodes is treated as a special one-byte
instruction. If the prebyte is misaligned, the O cycle is used as a program word
access for the prebyte; if the prebyte is aligned, the O cycle appears as a free
cycle. If the remainder of the instruction consists of an odd number of bytes, an-
other O cycle is required some time before the instruction is completed. If the O
cycle for the prebyte is treated as a P cycle, any subsequent O cycle in the same
instruction is treated as an f cycle; if the O cycle for the prebyte is treated as an
f cycle, any subsequent O cycle in the same instruction is treated as a P cycle.
Optional cycles used for program word accesses can be extended to two bus
cycles if the MCU is operating with an 8-bit external data bus and the program
is stored in external memory. There can be additional stretching when the ad-
dress space is assigned to a chip-select circuit programmed for slow memory.
Optional cycles used as free cycles are never stretched.
These cycles are extended to two bus cycles if the MCU is operating with an 8-
bit external data bus and the program is stored externally. There can be addi-
tional stretching when the address space is assigned to a chip-select circuit pro-
grammed for slow memory.
circuit programmed for slow memory.
erating with an 8-bit external data bus and the corresponding data is stored in
external memory. There can be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow memory. These cycles
are also stretched if they correspond to misaligned accesses to memory that is
not designed for single-cycle misaligned access.
lect circuit programmed for slow memory.
operating with an 8-bit external data bus and the SP is pointing to external mem-
ory. There can be additional stretching if the address space is assigned to a
chip-select circuit programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses to a memory that is not de-
signed for single cycle misaligned access. The internal RAM is designed to al-
low single cycle misaligned word access.
lect circuit programmed for slow memory.
erating with an 8-bit external data bus and the corresponding data is stored in
external memory. There can be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow memory. These cycles
are also stretched if they correspond to misaligned access to a memory that is
not designed for single-cycle misaligned access.
select circuit programmed for slow memory.
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
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