Motorola HC12 Refrence Manual page 430

Loop primitive 4-5, 5-16, 6-70 to 6-71,
6-92 to 6-93, 6-200, 6-202
Offset values 5-13, 5-16
Offsets 3-4
Short 4-4 to 4-5, 5-13, 6-26, 6-28 to 6-30,
6-32 to 6-34, 6-37 to 6-44, 6-46, 6-50 to 6-51
Signed 5-13, 6-30, 6-32, 6-37, 6-40,
6-107 to 6-108, 6-111, 6-114
Simple 5-13, 6-26, 6-28 to 6-29, 6-41 to 6-43,
6-50 to 6-51, 6-104 to 6-106, 6-115 to 6-117,
6-120 to 6-121
Subroutine 5-17, 6-49
Taken/not-taken cases 4-4, 6-7
Unary 5-13, 6-44, 6-46, 6-118 to 6-119
Unsigned 5-13, 6-33 to 6-34, 6-38 to 6-39,
6-109 to 6-110, 6-112 to 6-113
BRCLR instruction 6-45
BRN instruction 6-46
BRSET instruction 6-47
BSET instruction 6-48
BSR instruction 4-3, 6-49
Bus cycles 6-5
Bus structure B-4
BVC instruction 6-50
BVS instruction 6-51
Byte moves 6-144
Byte order in memory 2-5
Byte-sized instructions 4-4 to 4-5
C status bit 2-5, 6-19 to 6-26, 6-28, 6-33 to 6-34,
6-38 to 6-39, 6-54, 6-69, 6-72 to 6-74,
6-78 to 6-79, 6-81 to 6-86, 6-95 to 6-98,
6-104 to 6-105, 6-109 to 6-110,
6-112 to 6-113, 6-131 to 6-140,
6-142 to 6-143, 6-168, 6-170 to 6-175,
6-179 to 6-182, 6-193 to 6-195
CALL instruction 3-12, 4-3, 5-17, 6-52,
10-2 to 10-3, B-16, C-4 to C-5
Case statements C-4
CBA instruction 6-53
Changes in execution flow 4-2 to 4-5,
6-102 to 6-103, 6-176 to 6-178, 6-196,
7-1 to 7-6
CLC instruction 6-54
Clear instructions 5-6, 6-56 to 6-58
Cleared 1-3
CLI instruction 6-55
Clock monitor reset 7-3
CLR instruction 6-56
CLRA instruction 6-57
CLRB instruction 6-58
CLV instruction 6-59
CMPA instruction 6-60
MOTOROLA
I-2
C
CMPB instruction 6-61
Code size B-10
COM instruction 6-62
COMA instruction 6-63
COMB instruction 6-64
Compare instructions 5-5, 6-53, 6-60 to 6-61,
6-65 to 6-68
Complement instructions 5-6, 6-62 to 6-64
Computer operating properly monitor 7-3
Condition codes instructions 5-21, 6-18,
6-54 to 6-55, 6-59, 6-153, 6-156, 6-162,
6-182 to 6-184, 6-198, 6-203 to 6-204, B-15
Condition codes register 2-1, 2-3, 6-18,
6-54 to 6-55, 6-59, 6-90, 6-128, 6-153, 6-156,
6-162, 6-177, 6-183 to 6-185, 6-198,
6-203 to 6-204, 6-206 to 6-208, C-4
C status bit 2-5, 6-19 to 6-26, 6-28, 6-33 to 6-34,
6-38 to 6-39, 6-54, 6-69, 6-72 to 6-74,
6-78 to 6-79, 6-81 to 6-86, 6-95 to 6-98,
6-104 to 6-105, 6-109 to 6-110,
6-112 to 6-113, 6-131 to 6-140,
6-142 to 6-143, 6-168, 6-170 to 6-175,
6-179 to 6-182, 6-193 to 6-195
H status bit 2-4, 6-8, 6-11 to 6-14, 6-69
I mask bit 2-4, 6-18, 6-55, 6-183, 6-196, 6-205,
6-213, 7-2, 7-4
Manipulation 5-21, 6-18, 6-54 to 6-55, 6-59,
6-153, 6-182 to 6-184, 6-198, 6-204
N status bit 2-4, 6-41, 6-43, 6-115, 6-117
S control bit 2-3, 6-189
Stacking 6-156, 6-162
V status bit 2-4, 6-50 to 6-51, 6-59,
6-120 to 6-121, 6-166 to 6-169, 6-184
X mask bit 2-3, 6-90, 6-162, 6-177, 6-189, 6-198,
6-203, 6-213, 7-2, 7-4
Z status bit 2-4, 6-29, 6-42, 6-81 to 6-84,
6-100 to 6-101, 6-106, 6-116,
6-139 to 6-140, 6-142 to 6-143
Conditional 16-bit read cycle 6-7
Conditional 8-bit read cycle 6-7
Conditional 8-bit write cycle 6-7
Conserving power 5-21, 6-189
Constant indirect indexed addressing mode 3-7
Constant offset indexed addressing mode
3-6 to 3-7
Conventions 1-3
COP reset 7-3
CPD instruction 6-65
CPS instruction 6-66
CPU wait 6-213
CPX instruction 6-67
CPY instruction 6-68
Cycle code letters 6-5
Cycle counts B-9
CPU12
REFERENCE MANUAL