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INCB
(B) + $01 ⇒ B
Operation:
Description:
Add one to the content of accumulator B.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus al-
lowing the INC instruction to be used as a loop counter in multiple-preci-
sion computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on
two's complement values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
–
N:
Z:
V:
Addressing Modes, Machine Code, and Execution Times:
Source Form
INCB
MOTOROLA
6-98
Increment B
X
H
I
N
Z
∆
∆
–
–
–
Set if MSB of result is set; cleared otherwise.
Set if result is $00; cleared otherwise.
Set if there is a two's complement overflow as a result of the opera-
tion; cleared otherwise. Two's complement overflow occurs if and
only if (B) was $7F before the operation.
Address Mode
INH
INSTRUCTION GLOSSARY
V
C
∆
–
Object Code
52
INCB
Cycles
Access Detail
1
O
CPU12
REFERENCE MANUAL
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