Motorola HC12 Refrence Manual page 9

Table
3-1 M68HC12 Addressing Mode Summary............................................................ 3-1
3-2 Summary of Indexed Operations ..................................................................... 3-6
3-3 PC Offsets for Move Instructions ................................................................... 3-11
5-1 Load and Store Instructions ............................................................................. 5-2
5-2 Transfer and Exchange Instructions ................................................................ 5-3
5-3 Move Instructions ............................................................................................. 5-3
5-4 Addition and Subtraction Instructions............................................................... 5-4
5-5 BCD Instructions .............................................................................................. 5-4
5-6 Decrement and Increment Instructions ............................................................ 5-5
5-7 Compare and Test Instructions ........................................................................ 5-5
5-8 Boolean Logic Instructions ............................................................................... 5-6
5-9 Clear, Complement, and Negate Instructions .................................................. 5-6
5-10 Multiplication and Division Instructions ............................................................ 5-7
5-11 Bit Test and Manipulation Instructions ............................................................. 5-7
5-12 Shift and Rotate Instructions ............................................................................ 5-8
5-13 Fuzzy Logic Instructions................................................................................. 5-10
5-14 Minimum and Maximum Instructions.............................................................. 5-11
5-15 Multiply and Accumulate Instructions............................................................. 5-12
5-16 Table Interpolation Instructions ...................................................................... 5-12
5-17 Short Branch Instructions............................................................................... 5-14
5-18 Long Branch Instructions ............................................................................... 5-15
5-19 Bit Condition Branch Instructions ................................................................... 5-16
5-20 Loop Primitive Instructions ............................................................................. 5-16
5-21 Jump and Subroutine Instructions.................................................................. 5-17
5-22 Interrupt Instructions ...................................................................................... 5-18
5-23 Index Manipulation Instructions...................................................................... 5-19
5-24 Stacking Instructions ...................................................................................... 5-20
5-25 Pointer and Index Calculation Instructions..................................................... 5-21
5-26 Condition Codes Instructions ......................................................................... 5-21
5-27 STOP and WAIT Instructions ......................................................................... 5-22
5-28 Background Mode and Null Operation Instructions........................................ 5-22
7-1 CPU12 Exception Vector Map ......................................................................... 7-1
7-2 Stacking Order on Entry to Interrupts............................................................... 7-5
8-1 IPIPE[1:0] Decoding......................................................................................... 8-2
8-2 BDM Commands Implemented in Hardware.................................................. 8-10
8-3 BDM Firmware Commands............................................................................ 8-11
8-4 BDM Register Mapping .................................................................................. 8-11
8-5 Tag Pin Function ............................................................................................ 8-13
10-1 Mapping Precedence ..................................................................................... 10-2
A-1 Instruction Set Summary..................................................................................A-2
A-2 CPU12 Opcode Map ......................................................................................A-20
A-3 Indexed Addressing Mode Summary .............................................................A-22
A-4 Indexed Addressing Mode Postbyte Encoding (xb) .......................................A-23
CPU12
REFERENCE MANUAL
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