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FDIV
Operation:
(D)
Description:
Divides an unsigned 16-bit numerator in double accumulator D by an un-
signed 16-bit denominator in index register X, producing an unsigned
16-bit quotient in X, and an unsigned 16-bit remainder in D. If both the
numerator and the denominator are assumed to have radix points in the
same positions, the radix point of the quotient is to the left of bit 15. The
numerator must be less than the denominator. In the case of overflow
(denominator is less than or equal to the numerator) or division by zero,
the quotient is set to $FFFF, and the remainder is indeterminate.
FDIV is equivalent to multiplying the numerator by 2
ing 32 x 16-bit integer division. The result is interpreted as a binary-
weighted fraction, which resulted from the division of a 16-bit integer by
a larger 16-bit integer. A result of $0001 corresponds to 0.000015, and
$FFFF corresponds to 0.9998. The remainder of an IDIV instruction can
be resolved into a binary-weighted fraction by an FDIV instruction. The
remainder of an FDIV instruction can be resolved into the next 16 bits of
binary-weighted fraction by another FDIV instruction.
Condition Codes and Boolean Formulas:
S
–
Z:
V:
C:
Addressing Modes, Machine Code, and Execution Times:
Source Form
FDIV
CPU12
REFERENCE MANUAL
Fractional Divide
÷
(X) ⇒ X; Remainder ⇒ D
X
H
I
N
Z
∆
–
–
–
–
Set if quotient is $0000; cleared otherwise.
1 if X ≤ D
Set if the denominator was less than or equal to the numerator;
cleared otherwise.
X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise.
Address Mode
INH
INSTRUCTION GLOSSARY
V
C
∆
∆
Object Code
18 11
FDIV
16
and then perform-
Cycles
Access Detail
12
OffffffffffO
MOTOROLA
6-91
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