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Where n is the number of labels of a system output, S
the knowledge base, and F
The 8-bit B accumulator holds the iteration count n. Internal temporary registers hold
intermediate sums, 24 bits for the numerator and 16 bits for the denominator. This
makes this instruction suitable for n values up to 255 although eight is a more typical
value. The final long division is performed with a separate EDIV instruction immediate-
ly after the WAV instruction. The WAV instruction returns the numerator and denomi-
nator sums in the correct registers for the EDIV. (EDIV performs the unsigned division
Y = Y : D / X; remainder in D).
Execution time for this instruction depends on the number of iterations (labels for the
system output). WAV is interruptible so that worst case interrupt latency is not affected
by the execution time for the complete weighted average operation. WAV includes ini-
tialization for the 24-bit and 16-bit partial sums so the first entry into WAV looks differ-
ent than a resume from interrupt operation. The CPU12 handles this difficulty with a
pseudo-instruction (wavr), which is specifically intended to resume an interrupted
weighted average calculation. Refer to
wavr
for more detail.
9.6.1 Setup Prior to Executing WAV
Before executing the WAV instruction, index registers X and Y and accumulator B
must be set up. Index register X is a pointer to the S
address of the first singleton value in the knowledge base. Index register Y is a pointer
to the fuzzy outputs F
output. B is the iteration count n. The B accumulator must be set to the number of la-
bels for this system output.
9.6.2 WAV Interrupt Details
The WAV instruction includes an 8-cycle processing loop for each label of the system
output. Within this loop, the CPU checks whether a qualified interrupt request is pend-
ing. If an interrupt is detected, the current values of the internal temporary registers for
the 24-bit and 16-bit sums are stacked, the CPU registers are stacked, and the inter-
rupt is serviced.
A special processing sequence is executed when an interrupt is detected during a
weighted average calculation. This exit sequence adjusts the PC so that it points to
the second byte of the WAV object code ($3C), before the PC is stacked. Upon return
from the interrupt, the $3C value is interpreted as a wavr pseudo-instruction. The wavr
pseudo-instruction causes the CPU to execute a special WAV resumption sequence.
The wavr recovery sequence adjusts the PC so that it looks like it did during execution
of the original WAV instruction, then jumps back into the WAV processing loop. If an-
other interrupt occurs before the weighted average calculation finishes, the PC is ad-
justed again as it was for the first interrupt. WAV can be interrupted any number of
times, and additional WAV instructions can be executed while a WAV instruction is in-
terrupted.
CPU12
REFERENCE MANUAL
are fuzzy outputs from RAM. S
i
9.6.3 Cycle-by-Cycle Details for WAV and
. Y must have the address of the first fuzzy output for this system
i
FUZZY LOGIC SUPPORT
are the singleton positions from
i
and F
are 8-bit values.
i
i
singleton list. X must have the
i
MOTOROLA
9-23
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