Motorola HC12 Refrence Manual page 341

Table A-1 Instruction Set Summary (Continued)
Source
Form
(A) • (M) ⇒ A
ANDA opr
Logical And A with Memory
(B) • (M) ⇒ B
ANDB opr
Logical And B with Memory
(CCR) • (M) ⇒ CCR
ANDCC opr
Logical And CCR with Memory
ASL opr
b7
C
Arithmetic Shift Left
ASLA Arithmetic Shift Left Accumulator A
ASLB Arithmetic Shift Left Accumulator B
ASLD
b7
C
Arithmetic Shift Left Double
ASR opr
b7
Arithmetic Shift Right
ASRA Arithmetic Shift Right Accumulator A
ASRB Arithmetic Shift Right Accumulator B
BCC rel Branch if Carry Clear (if C = 0)
(M) • (mm) ⇒ M
BCLR opr , msk
Clear Bit(s) in Memory
BCS rel Branch if Carry Set (if C = 1)
BEQ rel Branch if Equal (if Z = 1)
BGE rel Branch if Greater Than or Equal
(if N ⊕ V = 0) (signed)
BGND Place CPU in Background Mode
see Background Mode section.
BGT rel Branch if Greater Than
(N ⊕ V) = 0) (signed)
(if Z
BHI rel
Branch if Higher
(if C Z = 0) (unsigned)
CPU12
REFERENCE MANUAL
Operation
0
b0
0
b0
A b7 B b0
b0
C
INSTRUCTION REFERENCE
Addr. Machine
Mode Coding (hex)
IMM 84 ii
DIR 94 dd
EXT B4 hh ll
IDX A4 xb
IDX1 A4 xb ff
IDX2 A4 xb ee ff
[D,IDX] A4 xb
[IDX2] A4 xb ee ff
IMM C4 ii
DIR D4 dd
EXT F4 hh ll
IDX E4 xb
IDX1 E4 xb ff
IDX2 E4 xb ee ff
[D,IDX] E4 xb
[IDX2] E4 xb ee ff
IMM 10 ii
EXT 78 hh ll
IDX 68 xb
IDX1 68 xb ff
IDX2 68 xb ee ff
[D,IDX] 68 xb
[IDX2] 68 xb ee ff
INH 48
INH 58
INH 59
EXT 77 hh ll
IDX 67 xb
IDX1 67 xb ff
IDX2 67 xb ee ff
[D,IDX] 67 xb
[IDX2] 67 xb ee ff
INH 47
INH 57
REL 24 rr 3/1
DIR 4D dd mm
EXT 1D hh ll mm
IDX 0D xb mm
IDX1 0D xb ff mm
IDX2 0D xb ee ff mm
REL 25 rr 3/1
REL 27 rr 3/1
REL 2C rr 3/1
INH 00
REL 2E rr 3/1
REL 22 rr 3/1
*
~
S X H I N Z V C
– – ∆ ∆
1 – – 0
3
3
3
3
4
6
6
– – ∆ ∆
1 – – 0
3
3
3
3
4
6
6
⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓
1
– – ∆ ∆ ∆
4 – –
3
4
5
6
6
1
1
– – ∆ ∆ ∆
1 – –
– – ∆ ∆ ∆
4 – –
3
4
5
6
6
1
1
– – – – – – –
– – ∆ ∆
4 – – 0
4
4
4
6
– – – – – – –
– – – – – – –
– – – – – – –
5 – – – – – – –
– – – – – – –
– – – – – – –
MOTOROLA
–
–
⇓
∆
∆
∆
–
–
–
–
–
–
–
–
A-3