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TBEQ
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC
Operation:
Description:
Tests the specified counter register A, B, D, X, Y, or SP. If the counter
register is zero, branches to the specified relative destination. TBEQ is
encoded into three bytes of machine code including a 9-bit relative offset
(–256 to +255 locations from the start of the next instruction).
DBEQ and IBEQ instructions are similar to TBEQ, except that the
counter is decremented or incremented rather than simply being tested.
Bits 7 and 6 of the instruction postbyte are used to determine which op-
eration is to be performed.
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TBEQ abdxys,rel9
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don't care), bit 5 selects branch on zero
(TBEQ – 0) or not zero (TBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 0:1 for TBEQ.
Count
Bits 2:0
Register
A
000
B
001
D
100
X
101
Y
110
SP
111
MOTOROLA
6-200
Test and Branch if Equal to Zero
X
H
I
N
Z
–
–
–
–
–
Address Mode
REL
04 lb rr
Source Form
(if offset is positive)
TBEQ A, rel9
04 40 rr
TBEQ B, rel9
04 41 rr
TBEQ D, rel9
04 44 rr
TBEQ X, rel9
04 45 rr
TBEQ Y, rel9
04 46 rr
TBEQ SP, rel9
04 47 rr
INSTRUCTION GLOSSARY
V
C
–
–
1
Object Code
Object Code
04 50 rr
04 51 rr
04 54 rr
04 55 rr
04 56 rr
04 57 rr
TBEQ
Cycles
Access Detail
3/3
PPP
Object Code
(if offset is negative)
CPU12
REFERENCE MANUAL
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