Motorola HC12 Refrence Manual page 18

Normally, an RTI instruction at the end of the interrupt service routine restores register
values that were present before the interrupt occurred. Since the CCR is stacked be-
fore the X bit is set, the RTI normally clears the X bit, and thus re-enables non-
maskable interrupts. While it is possible to manipulate the stacked value of X so that
X is set after an RTI, there is no software method to re-set X (and disable NMI) once
X has been cleared.
2.1.5.3 H Status Bit
The H bit indicates a carry from accumulator A bit 3 during an addition operation. The
DAA instruction uses the value of the H bit to adjust a result in accumulator A to correct
BCD format. H is updated only by the ABA, ADD, and ADC instructions.
2.1.5.4 I Mask Bit
The I bit enables and disables maskable interrupt sources. By default, the I bit is set
to one during reset. An instruction must clear the I bit to enable maskable interrupts.
While the I bit is set, maskable interrupts can become pending and are remembered,
but operation continues uninterrupted until the I bit is cleared.
When an interrupt occurs after interrupts are enabled, the I bit is automatically set to
prevent other maskable interrupts during the interrupt service routine. The I bit is set
after the registers are stacked, but before the interrupt vector is fetched.
Normally, an RTI instruction at the end of the interrupt service routine restores register
values that were present before the interrupt occurred. Since the CCR is stacked be-
fore the I bit is set, the RTI normally clears the I bit, and thus re-enables interrupts.
Interrupts can be re-enabled by clearing the I bit within the service routine, but imple-
menting a nested interrupt management scheme requires great care, and seldom im-
proves system performance.
2.1.5.5 N Status Bit
The N bit shows the state of the MSB of the result. N is most commonly used in two's
complement arithmetic, where the MSB of a negative number is one and the MSB of
a positive number is zero, but it has other uses. For instance, if the MSB of a register
or memory location is used as a status flag, the user can test status by loading an ac-
cumulator.
2.1.5.6 Z Status Bit
The Z bit is set when all the bits of the result are zeros. Compare instructions perform
an internal implied subtraction, and the condition codes, including Z, reflect the results
of that subtraction. The INX, DEX, INY, and DEY instructions affect the Z bit and no
other condition flags. These operations can only determine = and ≠.
2.1.5.7 V Status Bit
The V bit is set when two's complement overflow occurs as a result of an operation.
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