Motorola HC12 Refrence Manual page 35

4.3.1 Exceptions
Exceptions are events that require processing outside the normal flow of instruction
execution. CPU12 exceptions include four types of resets, an unimplemented opcode
trap, a software interrupt instruction, X-bit interrupts, and I-bit interrupts. All exceptions
use the same microcode, but the CPU follows different execution paths for each type
of exception.
CPU12 exception handling is designed to minimize the effect of queue operation on
context switching. Thus, an exception vector fetch is the first part of exception pro-
cessing, and fetches to refill the queue from the address pointed to by the vector are
interleaved with the stacking operations that preserve context, so that program access
time does not delay the switch. Refer to
detailed information.
4.3.2 Subroutines
The CPU12 can branch to (BSR), jump to (JSR), or CALL subroutines. BSR and JSR
are used to access subroutines in the normal 64-Kbyte address space. The CALL in-
struction is intended for use in MCUs with expanded memory capability.
BSR uses relative addressing mode to generate the effective address of the subrou-
tine, while JSR can use various other addressing modes. Both instructions calculate a
return address, stack the address, then perform three program word fetches to refill
the queue. The first two words fetched are queued during the second and third cycles
of the sequence. The third fetch cycle is performed in anticipation of a queue advance,
which may occur during the fourth cycle of the sequence. If the queue is not yet ready
to advance at that time, the third word of program information is held in the buffer.
Subroutines in the normal 64-Kbyte address space are terminated with a return from
subroutine (RTS) instruction. RTS unstacks the return address, then performs three
program word fetches from that address to refill the queue.
CALL is similar to JSR. MCUs with expanded memory treat 16 Kbytes of addresses
from $8000 to $BFFF as a memory window. An 8-bit PPAGE register switches mem-
ory pages into and out of the window. When CALL is executed, a return address is cal-
culated, then it and the current PPAGE value are stacked, and a new instruction-
supplied value is written to PPAGE. The subroutine address is calculated, then three
program word fetches are made from that address.
The RTC instruction is used to terminate subroutines in expanded memory. RTC un-
stacks the PPAGE value and the return address, then performs three program word
fetches from that address to refill the queue.
CALL and RTC execute correctly in the normal 64-Kbyte address space, thus provid-
ing for portable code. However, since extra execution cycles are required, routinely
substituting CALL/RTC for JSR/RTS is not recommended.
CPU12
REFERENCE MANUAL
SECTION 7 EXCEPTION PROCESSING
INSTRUCTION QUEUE
for
MOTOROLA
4-3