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IBNE
(Counter) + 1 ⇒ Counter
Operation:
If (Counter) not = 0, then (PC) + $0003 + Rel ⇒ PC
Description:
Add one to the specified counter register A, B, D, X, Y, or SP. If the
counter register has not been incremented to zero, branch to the speci-
fied relative destination. The IBNE instruction is encoded into three bytes
of machine code including a 9-bit relative offset (–256 to +255 locations
from the start of the next instruction).
DBNE and TBNE instructions are similar to IBNE except that the counter
is decremented or tested rather than being incremented. Bits 7 and 6 of
the instruction postbyte are used to determine which operation is to be
performed.
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
IBNE abdxys, rel9
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don't care), bit 5 selects branch on zero
(IBEQ – 0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 1:0 for IBNE.
Count
Bits 2:0
Register
A
B
D
X
Y
SP
CPU12
REFERENCE MANUAL
Increment and Branch if Not
Equal to Zero
X
H
I
N
Z
–
–
–
–
–
Address Mode
REL
Source Form
000
IBNE A, rel9
001
IBNE B, rel9
IBNE D, rel9
100
101
IBNE X, rel9
110
IBNE Y, rel9
111
IBNE SP, rel9
INSTRUCTION GLOSSARY
V
C
–
–
1
Object Code
04 lb rr
Object Code
(if offset is positive)
04 A0 rr
04 A1 rr
04 A4 rr
04 A5 rr
04 A6 rr
04 A7 rr
IBNE
Cycles
Access Detail
3/3
PPP
Object Code
(if offset is negative)
04 B0 rr
04 B1 rr
04 B4 rr
04 B5 rr
04 B6 rr
04 B7 rr
MOTOROLA
6-93
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