Motorola HC12 Refrence Manual page 110

BVC
If V = 0, then (PC) + $0002 + Rel ⇒ PC
Operation:
Simple branch
Description: Tests the V status bit and branches if V = 0.
BVC causes a branch when a previous operation on two's complement
binary values does not cause an overflow. That is, when BVC follows a
two's complement operation, a branch occurs when the result of the op-
eration is valid.
See
Condition Codes and Boolean Formulas:
S
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BVC rel8
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Branch
Test Mnemonic
r>m BGT
r≥m BGE
r=m BEQ
r≤m BLE
r<m BLT
r>m BHI
r≥m BHS/BCC
r=m BEQ
r≤m BLS
r<m BLO/BCS
Carry BCS
Negative BMI
Overflow BVS
r=0 BEQ
Always BRA
MOTOROLA
6-50
Branch if Overflow Cleared
3.7 Relative Addressing Mode
X H I N Z
– – – – –
Address Mode
REL
Opcode Boolean
⊕
Z + (N
2E V) = 0
⊕
2C N V = 0
27 Z = 1
⊕
Z + (N
2F V) = 1
⊕
2D N V = 1
C + Z = 0
22
24 C = 0
27 Z = 1
C + Z = 1
23
25 C = 1
25 C = 1
2B N = 1
29 V = 1
27 Z = 1
20 —
INSTRUCTION GLOSSARY
for details of branch execution.
V C
– –
Object Code
28 rr
Complementary Branch
Test Mnemonic
r≤m BLE
r<m BLT
r≠m BNE
r>m BGT
r≥m BGE
r≤m BLS
r<m BLO/BCS
r≠m BNE
r>m BHI
r≥m BHS/BCC
No Carry BCC
Plus BPL
No Overflow BVC
r≠0 BNE
Never BRN
BVC
Cycles Access Detail
1
3/1
PPP/P
Opcode Comment
2F Signed
2D Signed
26 Signed
2E Signed
2C Signed
23 Unsigned
25 Unsigned
26 Unsigned
22 Unsigned
24 Unsigned
24 Simple
2A Simple
28 Simple
26 Simple
21 Unconditional
CPU12
REFERENCE MANUAL