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8.3.1.3 st1_add, st1_dat Registers
These registers contain address and data for the first stage of the reconstructed in-
struction queue.
8.3.1.4 st2_add, st2_dat Registers
These registers contain address and data for the final stage of the reconstructed in-
struction queue. When the IPIPE[1:0] signals indicate that an instruction is starting to
execute, the address and opcode can be found in these registers.
8.3.2 Reconstruction Algorithm
This section describes in detail how to use IPIPE[1:0] signals and status storage reg-
isters to perform queue reconstruction. An "is_full" flag is used to indicate when the
fetch_add and fetch_dat buffer registers contain information. The use of the flag is ex-
plained more fully in subsequent paragraphs.
Typically, the first few cycles of raw capture data are not useful because it takes sev-
eral cycles before an instruction propagates to the head of the queue. During these
first raw cycles, the only meaningful information available are data movement signals.
Information on the external address and data buses during this setup time reflects the
actions of instructions that were fetched before data collection started.
In the special case of a reset, there is a five cycle sequence (VfPPP) during which the
reset vector is fetched and the instruction queue is filled, before execution of the first
instruction begins. Due to the timing of the switchover of the IPIPE[1:0] pins from their
alternate function as mode select inputs, the status information on these two pins may
be erroneous during the first cycle or two after the release of reset. This is not a prob-
lem because the status is correct in time for queue reconstruction logic to correctly rep-
licate the queue.
Before starting to reconstruct the queue, clear the is_full flag to indicate that there is
no meaningful information in the fetch_add and fetch_dat buffers. Further movement
of information in the instruction queue is based on the decoded status on the
IPIPE[1:0] signals at the rising edges of E.
8.3.2.1 LAT Decoding
On a latch cycle, check the is_full flag. If and only if is_full = 0, transfer the address
and data from the previous bus cycle (in_add and in_dat) into the fetch_add and
fetch_dat registers respectively. Then, set the is_full flag. The usual reason for a latch
request instead of an advance request is that the previous instruction ended with a sin-
gle aligned byte of program information in the last stage of the instruction queue. Since
the odd half of this word still holds the opcode for the next instruction, the queue can-
not advance on this cycle. However, the cycle to fetch the next word of program infor-
mation has already started and the data is on its way.
CPU12
REFERENCE MANUAL
DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-5
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