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JMP instruction 4-5, 6-102
JSR instruction 4-3, 6-103
Jump instructions 5-17
Jumps 4-5
Knowledge base 9-2
LBCC instruction 6-104
LBCS instruction 6-105
LBEQ instruction 6-106
LBGE instruction 6-107
LBGT instruction 6-108
LBHI instruction 6-109
LBHS instruction 6-110
LBLE instruction 6-111
LBLO instruction 6-112
LBLS instruction 6-113
LBLT instruction 6-114
LBMI instruction 6-115
LBNE instruction 6-116
LBPL instruction 6-117
LBRA instruction 6-118
LBRN instruction 6-119
LBVC instruction 6-120
LBVS instruction 6-121
LDAA instruction 6-122
LDAB instruction 6-123
LDD instruction 6-124
LDS instruction 6-125
LDX instruction 6-126
LDY instruction 6-127
LEAS instruction 6-128, C-2, C-4
Least signficant byte 1-3
Least significant word 1-3
LEAX instruction 6-129, C-4
LEAY instruction 6-130, C-4
Legal label 6-3
Literal expression 6-3
Load instructions 5-1, 6-122 to 6-130
Logic level one 1-3
Logic level zero 1-3
Loop primitive instructions 4-5, 6-70 to 6-71,
6-92 to 6-93, 6-200, 6-202, A-25, B-13, C-3
Offset values 5-16
Postbyte encoding A-25
Low-power stop 5-21, 6-189
LSL instruction 6-131
LSL mnemonics 5-8
LSLA instruction 6-132
LSLB instruction 6-133
CPU12
REFERENCE MANUAL
J
K
L
LSLD instruction 6-134
LSR instruction 6-135
LSRA instruction 6-136
LSRB instruction 6-137
LSRD instruction 6-138
Maskable interrupts 7-1, 7-4
MAXA instruction 6-139
Maximum instructions 5-11, B-14
16-bit 6-81 to 6-82
8-bit 6-139 to 6-140
MAXM instruction 6-140, 9-1
MEM instruction 5-9, 6-141, 9-1, 9-9 to 9-13
Membership functions 9-2
Memory and addressing symbols 1-2
Memory expansion
Addressing 10-7
Bank switching 10-7
Overlay windows 10-7
Page registers 10-3, 10-7
MINA instruction 6-142, 9-1
Minimum instructions 5-11, B-14
16-bit 6-83 to 6-84
8-bit 6-142 to 6-143
MINM instruction 6-143
Misaligned instructions 4-4 to 4-5
Mnemonic 1-3
Mnemonic ranges 1-3
Most significant byte 1-3
Most significant word 1-3
MOVB instruction 6-144
Move instructions 5-3, 6-144 to 6-145, B-10, B-13
Destination 3-10
Multiple addressing modes 3-10
PC relative addressing 3-10
Reference index register 3-10
Source 3-10
MOVW instruction 6-145
MUL instruction 6-146
Multiple addressing modes
Bit manipulation instructions 3-11, 6-27, 6-48
Move instructions 3-10, 6-144 to 6-145
Multiplication instructions 5-7
16-bit 6-85 to 6-86
8-bit 6-146
Multiply and accumulate instructions 5-11, 6-80,
6-214
M68HC11 compatibility 3-2, B-1
M68HC11 instruction mnemonics B-1
N status bit 2-4, 6-41, 6-43, 6-115, 6-117
M
N
MOTOROLA
I-5
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