Motorola HC12 Refrence Manual page 287

8.2.1 Zero Encoding (0:0)
The 0:0 state at the rising edge of E indicates that there was no data movement in the
instruction queue during the previous cycle; the 0:0 state at the falling edge of E indi-
cates continuation of an instruction or interrupt sequence.
8.2.2 LAT — Latch Data from Bus Encoding (0:1)
Fetched program information has arrived, but the queue is not ready to advance. The
information is latched into the buffer. Later, when the queue does advance, stage 1 is
refilled from the buffer, or from the data bus if the buffer is empty. In some instruction
sequences, there can be several latch cycles before the queue advances. In these
cases, the buffer is filled on the first latch event and additional latch requests are ig-
nored.
8.2.3 ALD — Advance and Load from Data Bus Encoding (1:0)
The two-stage instruction queue is advanced by one word and stage 1 is refilled with
a word of program information from the data bus. The CPU requested the information
two bus cycles earlier but, due to access delays, the information was not available until
the E cycle immediately prior to the ALD.
8.2.4 ALL — Advance and Load from Latch Encoding (1:1)
The two-stage instruction queue is advanced by one word and stage 1 is refilled with
a word of program information from the buffer. The information was latched from the
data bus at the falling edge of a previous E cycle because the instruction queue was
not ready to advance when it arrived.
8.2.5 INT — Interrupt Sequence Encoding (0:1)
The E cycle starting at this E fall is the first cycle of an interrupt sequence. Normally
this cycle is a read of the interrupt vector. However, in systems that have interrupt vec-
tors in external memory and an 8-bit data bus, this cycle reads only the upper byte of
the 16-bit interrupt vector.
8.2.6 SEV — Start Instruction on Even Address Encoding (1:0)
The E cycle starting at this E fall is the first cycle of the instruction in the even (high
order) half of the word at the head of the instruction queue. The queue treats the $18
prebyte for instructions on page 2 of the opcode map as a special 1-byte, 1-cycle in-
struction, except that interrupts are not recognized at the boundary between the pre-
byte and the rest of the instruction.
8.2.7 SOD — Start Instruction on Odd Address Encoding (1:1)
The E cycle starting at this E fall is the first cycle of the instruction in the odd (low order)
half of the word at the head of the instruction queue. The queue treats the $18 prebyte
for instructions on page 2 of the opcode map as a special 1-byte, 1-cycle instruction,
except that interrupts are not recognized at the boundary between the prebyte and the
rest of the instruction.
CPU12
REFERENCE MANUAL
DEVELOPMENT AND DEBUG SUPPORT MOTOROLA
8-3