Table of Contents
Advertisement
SWI
(SP) – $0002 ⇒ SP; RTN
Operation:
(SP) – $0002 ⇒ SP; Y
(SP) – $0002 ⇒ SP; X
(SP) – $0002 ⇒ SP; B : A⇒ (M
(SP) – $0001 ⇒ SP; CCR ⇒ (M
1 ⇒ I
(SWI Vector) ⇒ PC
Description:
Causes an interrupt without an external interrupt service request. Uses
the address of the next instruction after SWI as a return address. Stacks
the return address, index registers Y and X, accumulators B and A, and
the CCR, decrementing the SP before each item is stacked. The I mask
bit is then set, the PC is loaded with the SWI vector, and instruction ex-
ecution resumes at that location. SWI is not affected by the I mask bit.
Refer to
Condition Codes and Boolean Formulas:
S
–
I:
Addressing Modes, Machine Code, and Execution Times:
Source Form
SWI
Notes:
1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A
variation of the sequence (VfPPP) is used for resets.
MOTOROLA
6-196
Software Interrupt
H
H
SECTION 7 EXCEPTION PROCESSING
X
H
I
N
Z
–
–
1
–
–
1; Set.
Address Mode
INH
INSTRUCTION GLOSSARY
⇒ (M
: RTN
H
L
(SP)
⇒ (M
: Y
: M
(SP + 1)
L
(SP)
⇒ (M
: X
: M
(SP + 1)
L
(SP)
: M
(SP + 1)
(SP)
)
(SP)
V
C
–
–
Object Code
3F
SWI
: M
(SP + 1)
)
)
)
)
for more information.
Cycles
Access Detail
9
VSPSSPSsP
CPU12
REFERENCE MANUAL
1
Advertisement
Table of Contents
