System Resetting And System Clock Generation Circuits - Panasonic JB-3300 Technical Manual

5.2 System Resetting and System Clock Generation Circuits
(a) System reset circuit
Two reset signals automatically reset when the power is turned on.
(1) System reset signal (RESET)
The leading voltage edge of the +5 V power is integrated by
register R9Y and capacitor C17. Its level is detected by the
8284A circuit, and is output as a reset signal.
The duration of the reset signal at this time is approximately
400 ms to 1.3 sec.
+5V od
. 8B284A
RES
+ 10
RESET RESET
Lo xreser
+5V
=
7
7 __
4s RES Input
a
" \ Detection Level
1.05 to 2.6 V
RESET
—_ 400 ms to.1.3s
Figure 5-1 System Resetting Circuit and Operation
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