Panasonic JB-3300 Technical Manual page 143

(ob) Address and data buses
Address Latch
Circuit
LS373
Al9
; » D Q » Address Bus
A1l3 AB19 to AB13
1G op—
LS244
Al2
) oe 1A Y . | >» Address Bus
A8
AB12 to AB8
0 jO—?
LS373
one » a » Address Bus
ADO AB7 to ABO
1G 0 O—?
____. *AENCPU
_S$245
| 1A 8B K » Data
ALE
DT/R DIR GoO——_
LSO4
DEN
Figure 5-4 Address and Data Buses
Of address bus lines ABO to AB19, ABO to AB7 (eight bits) and AB1i3 to
AB19 (seven bits) are fetched and output by the address latch enable
Signal (ALE), which is output by the MPU bus controller. Bits AB8 to
AB12 are output via the bus amplifier. AB13 to AB15 need not be
latched; in this circuit, however, they pass through an address latch
circuit.
In DMA operation, the level of the *AENCPU signal goes HIGH, which in
turn makes all address bus lines high impedance.
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