Panasonic JB-3300 Technical Manual page 196

Graphic data mix, data latch
The graphic data mix, data latch circuit combines the even address
with the odd address in the GRAPHIC display mode, and latches the
combined data. The data is latched at the rising edge of CLKI1, and
output to LCHGO to LCHG7.
Figure 5-51 shows a graphic data mix, data latch circuit diagram.
EVEN, ODD Memory
Oata Mix Buffer
LS373 LS374
L CHG 7
L. CHG 6
L CHG 5
L. CHG 4
L CHG 3
L CHG 2
LCHG 1
L CHG 0
(6-7H) EN EVEN
(5-5F) XGRAPHIC
ATB7
ATB6
ATBS
ATB4
ATB3
ATB2
ATBI
ATBO
(6-10C)
{(6-3F ) CLKI
Figure 5-51 Graphic Data Mix, Data Latch Circuit
Figure 5-52 shows an operation timing chart.
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