Panasonic JB-3300 Technical Manual page 233

(c)
(d)
(e)
(f)
As the table above shows, input signals 1Cl and 2Cl are output to 1Y
and 2Y respectively when A=H and B=L. This state is given if the
option slot of the equipment is used.
Input signals 1C2 and 2C2 are output to 1Y and 2Y respectively when
A=L and B=H. This state is given if the option slot of the extension
unit is used, and a gate and DIR signals delayed 150 ns by the 74LS31
are output.
The 74LS31 (5C) generates a DIR signal delayed by 150 ns.
The 74LS31 (6C) generates a gate signal delayed by 150 ns.
The 74LS74 (11B-2) generates a reset signal for the 74LS74 (11B-1).
The circuit in the dotted-line square in Figure 5-80 generates the
conditions of a gate and DIR signals.
The 74LS02 (10C-1) changes the direction of the data bus from A to B
for option memory read.
The 74LS02 (10C-2) changes the direction of the data bus from A to B
for option I/O read.
The 74LS02 (10C-3) changes the direction of the data bus from A to B
for extender read.
The 74LS20 (5D) generates a gate signal. This gate signal is put in
a high level when accessing the option memory, option I/O, and
extender card.
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