Panasonic JB-3300 Technical Manual page 191

(k)
VRAM data bus circuit
The VRAM data bus circuit consists of an even-numbered address memory
block and an odd-numbered address memory block. Each of these blocks
consists of 2 memory chips, 1 bus transceiver, and 2 data latches.
Figure 5-47 shows a VRAM data bus circuit block diagram.
(1)
(2)
VRAM
The VRAM has four 16K-word x 4-bit memory chips with a total
capacity of 32K bytes. The CPU or DMAC accesses the even-
address memory block of VRAM if the address is an even-numbered
address (XABO = 0), or the odd-address memory block of VRAM if
it 1s an odd-numbered address (XAB = 1). A bidirectional
transceiver (LS245) is provided between the VRAM data bus and
data bus lines VDO to VD7. When reading VRAM, data is trans-
ferred from the VRAM data bus to data bus lines VDO to VD7.
When writing to VRAM, data is transferred in the opposite
direction. The direction is controlled by the *VRAM WR signal.
CRTC access to VRAM
In accessing VRAM from CRTC, an even address (address n) and an
odd address (address n + 1) in VRAM are read Simultaneously, and
are latched to the first data latch at the rising edge of the
*CRT CAS1 signal.
In the CRTC cycle mode, VRAM is read twice by page mode read;
hence, the next even address (n + 2 address) and odd address (n
+ 3 address) are read, and latched to the second data latch at
the rising edge of the *CRT CASO signal.
Except when the display mode is other than TEXT 80x25, the
second and first memory addresses are the same; therefore, both
read data are the same.
The latched even address data is output to data bus lines CHBO
to CHB7, and the latched odd address data to data bus lines ATBO
to ATB7. The first data latch and second data latch are
Switched from one to the other by the EN EVEN signal. In the
graphic display mode, however, the first data latch is not
output to data bus lines ATBO to ATB7. Figures 5-48 and 5-49.
show operation timing diagrams.
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