Panasonic JB-3300 Technical Manual page 153

(b)
(c)
ROM circuit
The ROM circuit employs one ROM chip (equivalent to 27128) with a
16K-byte capacity (128K bits).
The ROM selection signal *ROMSEL is output from the memory address
decoder and fed directly to the Chip Select (CS) Pin on the ROM chip,
to output ROM data on the data bus upon receiving the memory read
Signal *XMEMR from the MPU.
ROM
Address ,
Bus 27128
ABi13 to AB
XABS ° ABE N AQ Data Bus
to XABO (
1
DB7 to DBO
A13
*ROMSEL q Cs
*XMEMR a OE
Figure 5-13 ROM Circuit
RAM circuit
RAM is accessed by the DMAC, or through DMAC refresh.
Figure 5-14 shows a functional block diagram of a RAM access
operation.
MPU addresses are converted into row and column addresses by the
address multiplex circuit and are input to the RAM synchronized with
the *RAS and *CAS timing Signals.
In normal RAM access by the MPU and DMAC, input and output data is
set in data bus lines DB7 to DBO after *RAS and *CAS are input.
RAM is refreshed every 16 us through Channel 0 of the DMAC. In RAM
refreshing, *DACKO is output from the DMAC, and the RAS address is
input to the RAM synchronized with the *RAS signal. Because *CAS is
not input, data is neither read nor written in.
The following operations are executed after RAM has been accessed by
the MPU. Figure 5-15 outlines operational timing.
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