Panasonic JB-3300 Technical Manual page 427

ENCODER/DECODER AND DATA SEPARATOR
General Description
The NDC 842 has been developed to facilitate the interface between the
magnetic disk drive and the controller. Incorporating all of the best
features of the Tl NDC 10 (MB15546), this interface chip is able to con-
nect the controller to a 5" disk drive and a floppy disk drive.
Principal Features
a. VFO data separation function
b. National PLL circuit and NDC 844/847 phase comparator are built-in.
c. MFM and FM recording method and response
d. Missing data pattern detection function
e. MFM write compensation support
f. 5 VDC single power supply
Operation of NDC 842
a. Reset input
(1) RST (RESET)
Clear all registers including the high active register and initia-
lize the NDC 842 chip.
b. Clock input
(1) 4FC (4F-CLOCK)
This clock is used for internal control and for the write circuit.
When set to half cycles, this clock is output as 2-F CLOCK.
(2) VCK (VCO-CLOCK)
This clock outputs the clock pulse for the VCO circuit. During the
read operation, the clock generated by this clock is output as
READ-CLOCK.
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