Panasonic JB-3300 Technical Manual page 236

Table 5-13 Option Slot Connector Signal Description (3/3)
Signal I/O Description
ALE
Address latch enable: Address latch signal
output from the processor. The I/O device
controllers and the memory use this control
Signal to synchronize their own operations.
The trailing edge of this signal latches the
address into the address latch.
AEN
Address latch: An active high line to indicate
that a DMA controller has been started and the
DMA controller has the bus access right.
This line is also used to switch the bus between
the processor and the DMA controller.
TC
Terminal count: An active high pulse to indicate
that the terminal count on the pertinent DMA
channel has reached zero.
CLK
Processor clock: The basic clock furnished to
the microprocessor. It is created by dividing
the master clock by three, and it has an interval
of 210 ns with a duty cycle of 33%. The clock
frequency is 4.77 MHz.
* TOCHRDY
T/O channel ready: Active low, this control
Signal is used by an I/O device to request the
processor or DMA controller to prolong the bus
cycle. The bus cycle is prolonged while this
line is low.
*TOCHCK
I/O channel check: Active low, this control
Signal provides the processor with parity (error)
information on memory or devices.
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