Panasonic JB-3300 Technical Manual page 182

(3)
VRAM access timing circuit
The VRAM access timing circuit controls the following:
O
O
VRAM access timing by the CRTC, CPU/DMAC
Refreshing
Oo VRAM address multiplexer
The VRAM access timing circuit is shown below.
(3F) XCLK| 3
(3F) CLK2 __afizmp=
—> (CRT SYNC)
r--~7~sjeB7 7 => ADV CRT (7E)
: 4 5
(5~ SF) XTEXTBO->
1 21D PRO
> CRT ADR (7G)(5-6D)
(5-6C)LCMAO © ' 1-—> 12NI
Q
CL
]
=> XCRT ADR
ALS74 lio 4 S00
q
(5-9A)RAMWAIT laf PR_]o PsfizmjpS—> x cpu ADR (7F)
D Q
(3G)XCLK3 U4 12N it SOO
~18 ofizm)pS—> « REFADR
ci? |
13
(I-10D) XRESET $
Figure 5-38 VRAM Access Timing Circuit
Output signals of the VRAM access timing circuit are:
a)
b)
Cc)
d)
CRT SYNC ..... LOW when VRAM access by the CRTC begins.
Makes CATADR HIGH.
ADV CRT ...... Sampling signal to detect the end of the CRT
cycle. Sampling starts at the rising edge of *CLK3. The
CRT cycle ends when ADV CRT goes LOW.
CRT ADR ...... HIGH when the VRAM is accessed by the CRTC
(CRT cycle). Enables the MA address output of the CRTC to
the VRAM address.
*CPU ADR ..... LOW when VRAM is accessed by the CPU (CPU
cycle). Enables the (X)AB address output of the CPU to VRAM
address.
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