Panasonic JB-3300 Technical Manual page 180

BSCLK
CLK | \
CLK4 e | | | |
SHIFT FFD
Input
SHIFT
Figure 5-35 Timing Generator Timing Chart
(2) CRTC CLOCK control circuit
The CRTC clock control circuit controls clock pulses to be fed
to the CLOCK input of the CRTC: clock pulses are 8 x BSCLK in
the TEXT 80x25 display mode, and 16 x BSCLK in the other display
modes. This circuit also generates the output enable signal EN
EVEN for display latch data. The CRTC clock control circuit is
shown below.
*TEXTS8O
CRT-CLEK
S
D Q < D Qe———_— *EN EVEN
CLK1 CK Qe4 Basic-CLK ——jCK Q+———-_ EN EVEN
R CLR
h
Figure 5-36 CRTC CLOCK Control Circuit
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