Panasonic JB-3300 Technical Manual page 159

5.7 I/O Address Decoder
This circuit decodes I/O addresses when the MPU performs I/O. Figure 5-19
shows the address map.
Table 5-3 shows the I/O command. The system uses indirect port addressing
in which MPU general register DX designates I/O instructions.
Figure 5-18 shows the functional block diagram.
ark x4 LSI38
AB2 Y XPRTCS (3-3E)
ABA
YI
XDSPCCS(4-!G)
(X6C)<4ABS XOSPDCS(4-1IG)
ABS 3P XEXPOCS(2-9F)
(x68) ABB
{
XFDCCS (3-3D)
(X68) ABS XFDOCS (3-3D)
XRSCCS (3-3E)
(K6A) XBS2
(XIOE) XAENCPU
(X7E) XAB5
(X7E) XABE6
(X7E) XAB7
XDMACS (X5F)
XINTCS (XIF)
XTIMCS (2-IE)
XPPICS (2-18)
XDMAPGST (X3G)
XWTNM! (X10)
xXxlow
(X5G) XCALOCS (3-3E)
XINIO (4-1H)
Figure 5-18 I/0 Address Decoder Circuit
o During DMP operation, *AENCPU goes HIGH, and I/O address decoding is
inhibited.
o During CPU operation, decoding is enabled or disabled as follows:
In I/O access, interrupt acknowledge, and halt cycles, *BS2 goes low,
and decoding is enabled.
In fetch cycle, memory read/write, and reverse cycles, decoding is
inhibited.
Il - 39