Panasonic JB-3300 Technical Manual page 185

Output signals are described below:
a)
b)
Cc)
dq)
e)
f)
*RAS ....4- A RAS input signal to VRAM; enabled at LOW. In
the CRT cycle mode, the +RAS pulse width is read twice by
page mode read; therefore, it is larger than the *RAS pulse
width in the refresh cycle mode or in the CPU cycle mode in
which Read/Write occurs only once.
MUX ...... A signal one pulse behind the RAS signal. It
switches a low address to a column address or vice versa in
the CRT cycle and CPU cycle modes. That is, low address
when MUX goes LOW, and column address when MUX goes HIGH.
*CPU CAS ..... A *CAS signal to be output when VRAM is
accessed in the CPU cycle mode.
*CRT CASO ..... The first *CAS output signal when VRAM is
accessed in the CRT cycle mode.
*CRT CASI] ..... The second *CAS output signal when VRAM is
accessed in the CRT cycle mode.
*CAS .....- A CAS input Signal to VRAM; enabled at low. Two
*CAS signals, i.e., *CRT CASO and *CRT CAS1, are output in
the CRT cycle mode. Only the *CPU CAS signal is output in
the CPU cycle mode. No *CAS signals are output in the
refresh cycle mode.
Figure 5-41 shows the timing chart.
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