Panasonic JB-3300 Technical Manual page 188

Each circuit operation is described below:
(1)
VRAM address MPX
Each address output to the VRAM address bus is controlled by the
*CPU ADR, *CRT ADR, and *REF ADR signals that are output by the
VRAM access timing circuit.
Selection of the RAS address or the
CAS address is made by the MUX output signal from the RAS/CAS
timing circuit.
VRAM addresses.
Table 5-4 shows addresses and corresponding
Table 5-4
PU Add AB| AB|AB/AB|AB| ABI AB|AB| AB] ABI AB| AB/ AB/ AB IAB
ress of 1} 21 3] 4! 5] 6] 7] 8} 9f10/121/12/13114
Cc 40x25 ~|ma|mMa|Ma|MA|Ma|Ma|Ma|MA|MA]MA|MA| MA] Ma |Ma
R TEXT oO} 1) 21 31 41 5) 6! 7/ 8] 9110/11/12 1413
T
C 80x25 —| cg |MA [MA MA| MA] MA) MA) MA MA MA MA| MA MA MA
TEXT 1/ 2} 3] 4} 5] 6] 7/1 8] 9110/11/12 1]13
A 320x200 ~|MA|MA|MA|MA|MA!MA!MA|MA|MA|MA|MA/MA|RA/RA
D GRAPHIC 0; 1| 2/ 3) 41 51 6] 7/1 8!) 9110/11/12 1/13
D
R 640x200 ~|mMa|MaA|MA|MA|MA|MA/MA|MA/MA|MA|MA|MA|RA/RA
E GRAPHIC Oo; 1/ 2! 3! 4] 5] 6] 7] 8! 9110/11/12 1/13
S
s 640x400 ~|MA|MA|MA|MA/MA)Ma|MaA|MaA|Ma|MA|MA)MA|RA/RA
GRAPHIC o| 1/ 2} 3) 41 5) 6! 7] 8} 9!10/121/12/13
REFRESH -| -(RFIRFIRFIRF RFIRF/RF|RF| -| -|/ -/| -| -
ADDRESS o| 1/ 2! 3! 4) 5] 6| 7
D-RAM c| RI R| RI RI RI RI RI Ri cl cl ciciec
ADDRESS *| 6] Oo] 1/1 2] 31 41 5] 6] 7] 1) 2] 3] 415
*; Chip select (ABO only is valid)
RF: REFRESH ADDRESS
CK: CKL3
C: Column address
R: Row address
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