Panasonic JB-3300 Technical Manual page 154

(1)
*RAMASEL are output.
(2)
MPU address is decoded, and RAM selection signals RAMSEL and
The *RAS signal is output from the MPU command signals *XMEMR
and *XMEMW, and the row address is input to the RAM from the
address multiplex circuit.
(3)
The row/column address switching signal RADMPX is output via the
delay device (LS31) from the *RAS signal, and the address is
switched to a column address.
(4)
*CASO or *CAS1 is selected and input to the RAM with the address
decoder output via the delay device (LS31) from RADMPX.
SOO
*XMEMR -————~ RAS
LS 31
LS 31
Genera-|_ [p>° MN CAS
<XMEMW tion . [—
" |
Circuit[ *RASO
5138
*RAS1 |
SEL A "
SEL B Genera-
* . tion
—
CAS
"RAMASEL
Circuit
*CAS1
*MWTC ———#| Timing
AEN Genera- ' 1
tion
.
RAS
DMARDY ———e|Circuit RASO |
'
A
AB17 to AB8 ——ccxess Bus
Address
RAM
RAM
XAB7 to XABO |_
Multi- [7
>
plexer 256K Bytes 256K Bytes
Expansion
WE
LS158x2
Z\
4
/\
*MEMW Genera- Ls51
tion *WE
Circuit
Data Bus
Data
DB7 to DBO <
>
Bus <
VD7 to
Buffer
VDO
LS245
Figure 5-14 RAM
34
Circuit Block Diagram