Panasonic JB-3300 Technical Manual page 166

INTR _|
*S0,*S1 |
v tf
T I
3 TW T4
T2 T3 TW T4 TI T2 T RO
fo
oh f
o
< TYPE VECTOR }>———
Figure 5-21 Interrupt Control Timing Chart
*S2
*INTA
Data Bus
DBO to DB/
5.9 Display Circuit
The display circuit controls the plasma display unit. Figure 5-22 shows a
block diagram of the display circuit.
follows:
(a)
Interface with the CPU:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Data bus transceiver
VRAM data latch
Display mode register
Status gate
CRTC parameter converter
Memory address decoder
WAIT circuit
a) Wait during VRAM access
b) Wait during I/O write
TI - 46
The blocks are described as