Panasonic JB-3300 Technical Manual page 178

(2) WAIT during I/O write
a) The WAIT circuit generates an I/O WAIT for an I/O write to
the Display Mode register (or the CRTC). The circuit sends
a WAIT to the CPU by means of *CRT WAIT.
b) *WRTE goes LOW, then HIGH in synchronization with CRTC. At
the rising edge of *WRTE, WAIT INH goes HIGH.
c) Then, *CRTC WAIT goes HIGH and the WAIT request ends. The
CPU also ends the I/O write operation.
ad) WAIT INH then goes LOW and the I/O WAIT circuit is enabled.
o VRAM access timing chart
*VRAMSEL
~~ _
\
oe
CPU CAS
wre ; t
<<
i
RAM WAIT
*CRT WAIT — |
o I/O write timing chart
*CRTC CS 7
:
mo
*WRTE
WAIT INH a )
S
IO WAIT
*CRT WAIT | |
Figure 5-33 WAIT Circuit Timing Chart
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