Panasonic JB-3300 Technical Manual page 167

(b) Display control circuit
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
Timing generator
a) Basic timing generator
b) CRTC clock control circuit
c) VRAM access timing circuit
ad) RAS and CAS timing circuit
CRTC
VRAM address controller
a) VRAM address multiplexer
b) CRTC address selector
c) Refreshing address counter
VRAM data transceiver data latch
a) VRAM
b) VRAM access by the CRTC
CHG and font data latch
Graphic data latch
Attribute decoder
Video data controller
a) First converter
b) Second converter
c) Third converter
CRTC control signal converter
a) DISPTMG cursor circuit
b) HSYNC circuit
c) VSYNC circuit
Blink timing circuit
Plasma output driver
Plasma reset control
Plasma interface signal
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