Panasonic JB-3300 Technical Manual page 158

CLK
DCLK
DREO
HRO
*SO0,*S1
*LOCK
HLDA
*AENCPU
* AEN
*AENDMA
AB19 to
ABO
DB7 to
DBO
ADSTB
DMAWAIT
*DACK
*XMEMR /
*XIOR
DMARDY
ENDDMA
rif| te []+3 [| tw
SI SI ) SO So
xo
Nw
Oo}
CS
a
WA
A (MPU no
»
t in ve
(MPU in operation) @ |
WP |
|
ly
|
ih
\I NLA
Se \t\ =
Lo \ /
MPU address
DMA address
DMA transfer data
\—x
[ 1 ©
MPU data | @ AI5~A
Lo
NO ©)
| 7
(8)
tL
(—--—*XMEMW /*XIOW)
Figure 5-17 DMA Operation Timing Chart